公开(公告)号：US08334571B2

公开(公告)日：2012-12-18

申请号：US12731562

申请日：2010-03-25

Applicant: Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Ming-Hsien Tsai ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01L23/60 ,  H01L23/64 ,  H01L29/08

CPC classification number: H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract translation: ESD保护装置包括设置在形成第一二极管的第二半导体类型的衬底中的第一半导体类型的第一阱。 第二半导体类型的第二阱形成在衬底中以与第一阱形成第二二极管。 第一半导体类型的第一多个掺杂区域形成在第一阱的上表面中。 第二半导体类型的第二多个掺杂区域形成在第一阱的上表面中，其与第一阱形成第三二极管。 多个STI区域形成在第一阱的上表面中。 每个STI区域设置在第一和第二半导体类型的掺杂区域之间。 当在第一或第二多个掺杂区域中的一个处接收ESD电压尖峰时，第三二极管提供电流旁路。

公开(公告)号：US20110260819A1

公开(公告)日：2011-10-27

申请号：US12766970

申请日：2010-04-26

Applicant: Tzu-Jin Yeh ,  Kal-Wen Tan ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H01F21/00

CPC classification number: H01F21/02 ,  H01F21/005 ,  H01F2021/125

Abstract: An integrated tunable inductor includes a primary inductor having a plurality of inductor turns, at least one closed loop eddy current coil proximate the primary inductor, and at least one variable resistor integrated in series with the eddy current coil.

Abstract translation: 集成可调电感器包括具有多个电感线圈的初级电感器，至少一个靠近初级电感器的闭环涡流线圈以及与涡流线圈串联集成的至少一个可变电阻器。

公开(公告)号：US20050023639A1

公开(公告)日：2005-02-03

申请号：US10632456

申请日：2003-07-31

Applicant: Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

Inventor： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

IPC: H01L21/02 ,  H01L27/08 ,  H01L29/00

CPC classification number: H01L28/10 ,  H01L27/08

Abstract: An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

Abstract translation: 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

公开(公告)号：US20150311159A1

公开(公告)日：2015-10-29

申请号：US14264076

申请日：2014-04-29

Applicant: Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Sa-Lly Liu ,  Tzong-Lin Wu

Inventor： Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Sa-Lly Liu ,  Tzong-Lin Wu

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5227 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: An electromagnetic bandgap (EBG) cell comprises a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wires on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell. The EBG cell further comprises a pair of through-substrate-vias (TSVs) above the plurality of first conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively, and a pair of micro bumps above a dielectric layer above the pair of TSVs, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die.

Abstract translation: 电磁带隙（EBG）单元包括在第一集成电路（IC）管芯下面的多个第一导线层，其中至少一个第一导线层上的导线各自连接到高电压源和低电压 电压源并且被定向以在EBG电池的底部形成第一网状结构。 EBG单元还包括在多个第一导线层上方的一对穿通基板通孔（TSV），其中该对TSV穿过第一IC管芯并且分别连接到高电压源和低压源 以及在所述一对TSV上方的电介质层上方的一对微凸块，其中所述微凸块将所述第一IC管芯的TSV与形成在第二IC管芯上的​​多个第二导线层连接。

公开(公告)号：US08848390B2

公开(公告)日：2014-09-30

申请号：US13028270

申请日：2011-02-16

Applicant: Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC: H05K1/11 ,  H05K1/14 ,  H01L23/48 ,  H01L25/065 ,  H01Q1/22 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/48 ,  H01L23/645 ,  H01L2225/06531 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01Q1/2283 ,  H01L2924/00

Abstract: A multi-chip module includes a chip stack package including at least one pair of stacked dies, the dies having overlapping opposing faces, and at least one capacitive proximity communication (CPC) interconnect between the pair of stacked dies. The CPC interconnect includes a first capacitor plate at a first one of the overlapping opposing faces and a second capacitor plate at a second one of the overlapping opposing faces spaced from and aligned with the first capacitor plate. The CPC interconnect further includes an inductive element connected in series with the first capacitor plate and second capacitor plate, wherein the capacitor plates form part of a capacitor and the capacitor cooperates with the inductor element to form a LC circuit having a resonant frequency.

Abstract translation: 多芯片模块包括芯片堆叠封装，其包括至少一对堆叠的裸片，所述裸片具有重叠的相对面，以及在所述一对堆叠裸片之间的至少一个电容邻近通信（CPC）互连。 CPC互连包括在重叠相对面中的第一个处的第一电容器板和与第一电容器板间隔开并与第一电容器板对准的第二个重叠相对面中的第二电容器板。 CPC互连还包括与第一电容器板和第二电容器板串联连接的电感元件，其中电容器板形成电容器的一部分，并且电容器与电感器元件配合以形成具有谐振频率的LC电路。

公开(公告)号：US08830011B2

公开(公告)日：2014-09-09

申请号：US13282642

申请日：2011-10-27

Applicant: Jun-De Jin ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Tzu-Jin Yeh

IPC: H03H7/075 ,  H03H7/01

CPC classification number: H03H7/075 ,  H03H7/1758

Abstract: A band-pass filter includes an input node coupled to receive an oscillating input signal, an output node, and a first LC resonator coupled to a first node coupled between the input node and the output node and to a first power supply node coupled to provide a first voltage. The first LC resonator includes a first capacitor, and a first inductor coupled in series with the first capacitor. The output node is coupled to output a filtered response signal that includes at least one zero based on the oscillating input signal and the first LC resonator.

Abstract translation: 带通滤波器包括耦合以接收振荡输入信号的输入节点，输出节点和耦合到耦合在输入节点和输出节点之间的第一节点的第一LC谐振器和耦合到第一电源节点的第一电源节点， 第一电压。 第一LC谐振器包括第一电容器和与第一电容器串联耦合的第一电感器。 输出节点被耦合以输出基于振荡输入信号和第一LC谐振器包括至少一个零的滤波响应信号。

公开(公告)号：US08742871B2

公开(公告)日：2014-06-03

申请号：US13044619

申请日：2011-03-10

Applicant: Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

IPC: H03H7/01 ,  H03H7/00

CPC classification number: H03H7/09 ,  H03H7/075 ,  H03H7/1758 ,  H03H2001/0078

Abstract: A bandpass filter comprises a first capacitor, a second capacitor, a third capacitor and at least two resonators. The first and second capacitors are coupled in parallel with each other, and each of the first and second capacitors includes an input. The third capacitor is coupled between the first capacitor and the second capacitor at their respective inputs. The at least two resonators are coupled in parallel with the first capacitor and the second capacitor and are positioned adjacent to each other at a distance such that the at least one component of the resonators are electromagnetically coupled together to provide three (3) transmission zeros.

Abstract translation: 带通滤波器包括第一电容器，第二电容器，第三电容器和至少两个谐振器。 第一和第二电容器彼此并联耦合，并且第一和第二电容器中的每一个包括输入端。 第三电容器在它们各自的输入处耦合在第一电容器和第二电容器之间。 所述至少两个谐振器与第一电容器和第二电容器并联耦合并且以一定距离彼此相邻地定位，使得谐振器的至少一个分量电磁耦合在一起以提供三（3）个传输零点。

公开(公告)号：US08627253B2

公开(公告)日：2014-01-07

申请号：US12766732

申请日：2010-04-23

Applicant: Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

Inventor： Tzu-Jin Yeh ,  Kal-Wen Tan ,  Chewn-Pu Jou ,  Sally Liu ,  Fu-Lung Hsueh

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/82

Abstract: In accordance with an embodiment, a method for substrate noise analysis comprises using a first processor based system, creating and simulating a circuit schematic comprising a multi-terminal model of a transistor, and thereafter, creating a layout based on properties represented in the circuit schematic and simulation results of the simulating. The multi-terminal model comprises a source terminal, a gate terminal, a drain terminal, a body terminal, and a guard-ring terminal.

Abstract translation: 根据实施例，用于衬底噪声分析的方法包括使用基于第一处理器的系统，创建和模拟包括晶体管的多端子模型的电路原理图，然后基于电路原理图中所示的特性创建布局 和仿真结果的模拟。 多端子模型包括源极端子，栅极端子，漏极端子，主体端子和保护环端子。

公开(公告)号：US08610494B1

公开(公告)日：2013-12-17

申请号：US13494263

申请日：2012-06-12

Applicant: Jun-De Jin ,  Tzu-Jin Yeh

Inventor： Jun-De Jin ,  Tzu-Jin Yeh

IPC: H03B1/00

CPC classification number: H03H7/0115 ,  H03H7/1758 ,  H03H11/48

Abstract: Some embodiments relate to a band-pass filter arranged in a ladder-like structure. The band-pass filter includes respective inductor-capacitor (LC) resonators arranged on respective rungs of the ladder-like structure. Respective matching circuits are arranged on a leg of the ladder-like structure between neighboring rungs.

Abstract translation: 一些实施例涉及布置成阶梯状结构的带通滤波器。 带通滤波器包括布置在阶梯状结构的各个梯级上的相应的电感器 - 电容器（LC）谐振器。 相应的匹配电路布置在相邻梯级之间的梯状结构的腿上。

公开(公告)号：US08451033B2

公开(公告)日：2013-05-28

申请号：US12967160

申请日：2010-12-14

Applicant: Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

Inventor： Po-Yi Wu ,  Hsieh-Hung Hsieh ,  Ho-Hsiang Chen ,  Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03B19/00

CPC classification number: H03B19/00

Abstract: A millimeter-wave wideband frequency doubler stage for use in a distributed frequency doubler includes: a differential input pair of transistors, each transistor having respective gate, drain and source terminals, wherein the source terminals are coupled together to a first power supply node and the drain terminals are coupled together at a first node to a second power supply node; first and second pairs of bandpass gate lines coupled to the gate terminals of the transistors; and a pair of bandpass drain lines coupled to the drain terminals of the transistors.

Abstract translation: 用于分布式倍频器的毫米波宽带倍频器级包括：差分输入对晶体管，每个晶体管具有相应的栅极，漏极和源极端子，其中源极端子耦合到第一电源节点，并且 漏极端子在第一节点耦合到第二电源节点; 耦合到晶体管的栅极端子的第一和第二对带通栅极线; 以及耦合到晶体管的漏极端子的一对带通漏极线。