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    LOW POWER ACTIVE FILTER
    2.
    发明申请
    LOW POWER ACTIVE FILTER 有权
    低功率有源滤波器

    公开(公告)号：US20130328623A1

    公开(公告)日：2013-12-12

    申请号：US13494263

    申请日：2012-06-12

    Applicant: Jun-De Jin ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Tzu-Jin Yeh

    IPC: H03H11/04 ,  H03H7/075

    CPC classification number: H03H7/0115 ,  H03H7/1758 ,  H03H11/48

    Abstract: Some embodiments relate to a band-pass filter arranged in a ladder-like structure. The band-pass filter includes respective inductor-capacitor (LC) resonators arranged on respective rungs of the ladder-like structure. Respective matching circuits are arranged on a leg of the ladder-like structure between neighboring rungs.

    Abstract translation: 一些实施例涉及布置成阶梯状结构的带通滤波器。 带通滤波器包括布置在阶梯状结构的各个梯级上的相应的电感器 - 电容器（LC）谐振器。 相应的匹配电路布置在相邻梯级之间的梯状结构的腿上。

    Through chip coupling for signal transport
    3.
    发明授权
    Through chip coupling for signal transport 有权
    通过芯片耦合进行信号传输

    公开(公告)号：US09397729B2

    公开(公告)日：2016-07-19

    申请号：US12946072

    申请日：2010-11-15

    Applicant: Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    Inventor： Tzu-Jin Yeh ,  Hsieh-Hung Hsieh ,  Jun-De Jin ,  Ming Hsien Tsai ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

    IPC: H04B5/00

    CPC classification number: H04B5/0081

    Abstract: Through-chip coupling is utilized for signal transport, where an interface is formed between a first coil on a first integrated circuit (IC) chip and a second coil on a second IC chip. The first coil is coupled to an antenna. The second coil is coupled to an amplifier circuit. The second coil is not in direct contact with the first coil. The first coil and the second coil communicatively transmit signals between the antenna and the first amplifier circuit.

    Abstract translation: 芯片耦合用于信号传输，其中在第一集成电路（IC）芯片上的第一线圈和第二IC芯片上的第二线圈之间形成接口。 第一线圈耦合到天线。 第二线圈耦合到放大器电路。 第二线圈不与第一线圈直接接触。 第一线圈和第二线圈在天线和第一放大器电路之间通信地传送信号。

    Integrated passive device filter with fully on-chip ESD protection
    4.
    发明授权
    Integrated passive device filter with fully on-chip ESD protection 有权
    集成无源器件滤波器，具有完全片上ESD保护

    公开(公告)号：US09093977B2

    公开(公告)日：2015-07-28

    申请号：US13562571

    申请日：2012-07-31

    Applicant: Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Ming Hsien Tsai ,  Tzu-Jin Yeh

    IPC: H02H9/00 ,  H03H7/40 ,  H02H9/04 ,  H01L23/60 ,  H01L23/64 ,  H01L23/522

    CPC classification number: H03H7/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/60 ,  H01L23/64 ,  H01L2924/0002 ,  H02H9/04 ,  H02H9/046 ,  Y10T29/49117 ,  H01L2924/00

    Abstract: The present disclosure relates to an on-chip electrostatic discharge (ESD) protection circuit that may be reused for a variety of integrated circuit (IC) applications. Both inductor-capacitor (LC) parallel resonator and shunt inductor (connected to ground) are used as ESD protection circuits and also as a part of an impedance matching network for a given IC application. The ESD LC resonator can be designed with a variety of band pass filter (BPF) topologies. On-chip ESD protection circuit allows for co-optimization ESD and BPF performance simultaneously, a fully on-chip ESD solution for integrated passive device (IPD) processes, eliminates a need for active ESD device protection, additional processes to support off-chip ESD protection, reduces power consumption, and creates a reusable BPF topology.

    Abstract translation: 本公开涉及可以重用于各种集成电路（IC）应用的片上静电放电（ESD）保护电路。 电感 - 电容（LC）并联谐振器和并联电感（连接到地）均用作ESD保护电路，也可用作给定IC应用的阻抗匹配网络的一部分。 ESD LC谐振器可以设计有各种带通滤波器（BPF）拓扑。 片上ESD保护电路允许同时优化ESD和BPF性能，用于集成无源器件（IPD）工艺的完全片上ESD解决方案，无需主动ESD器件保护，另外还支持片外ESD保护 保护，降低功耗，并创建可重用的BPF拓扑。

    ON-CHIP FERRITE BEAD INDUCTOR
    5.
    发明申请
    ON-CHIP FERRITE BEAD INDUCTOR 有权
    片芯铁素体电极

    公开(公告)号：US20130207230A1

    公开(公告)日：2013-08-15

    申请号：US13372873

    申请日：2012-02-14

    Applicant: Jun-De Jin ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Tzu-Jin Yeh

    IPC: H01L27/06 ,  H01L21/02

    CPC classification number: H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

    Abstract translation: 一种具有原位芯片级铁氧体磁珠电感器的半导体结构及其形成方法。 实施例包括基板，形成在基板上的第一介电层，形成在第一介电层上的下铁氧体层，以及与该结构中的下铁氧体层间隔开的上铁氧体层。 第一金属层可以形成在下铁素体层上方，第二金属层形成在上铁氧体层下面，其中至少第一或第二金属层具有包括多匝的线圈构型。 至少一个第二电介质层可以设置在第一和第二金属层之间。 铁氧体磁珠电感器具有小的外形尺寸，并且可以使用BEOL工艺来形成。

    Power cell, power cell circuit for a power amplifier and a method of making and using a power cell
    6.
    发明授权
    Power cell, power cell circuit for a power amplifier and a method of making and using a power cell 有权
    功率单元，功率放大器的功率单元电路以及制造和使用功率单元的方法

    公开(公告)号：US09490248B2

    公开(公告)日：2016-11-08

    申请号：US13753995

    申请日：2013-01-30

    Applicant: Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

    Inventor： Tzu-Jin Yeh ,  Chewn-Pu Jou ,  Jun-De Jin

    IPC: H01L29/66 ,  H01L29/772 ,  H01L27/06 ,  H03K17/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L27/0629 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/66484 ,  H01L29/66636 ,  H01L29/7832 ,  H03K17/102 ,  H03K2217/0018

    Abstract: A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

    Abstract translation: 一种功率单元，包括形成在基板中的具有第一掺杂剂类型的隔离区域。 功率单元还包括具有不同于在隔离区上形成的第一掺杂剂类型的第二掺杂剂型的底栅和在底栅上形成的具有第一掺杂剂类型的沟道层。 功率单元还包括在沟道层中形成的具有第一掺杂剂类型的源极/漏极区域和形成在沟道层和源极/漏极区域周围的具有第二掺杂剂类型的第一阱区域，以及与第一阱区域电连接的第一阱区域 底门 功率单元还包括具有第一掺杂剂类型的第二阱区，该第二阱区形成在沟道层周围并与隔离区接触并形成在沟道层上的栅极结构。

    High-k transformers extending into multiple dielectric layers
    7.
    发明授权
    High-k transformers extending into multiple dielectric layers 有权
    高k变压器延伸到多个电介质层

    公开(公告)号：US09424970B2

    公开(公告)日：2016-08-23

    申请号：US12955527

    申请日：2010-11-29

    Applicant: Jun-De Jin ,  Tzu-Jin Yeh

    Inventor： Jun-De Jin ,  Tzu-Jin Yeh

    IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00

    CPC classification number: H01F5/003 ,  H01F27/2804 ,  H01F2017/0046 ,  H01F2027/2809

    Abstract: A device includes a first plurality of dielectric layers over a substrate and a second plurality of dielectric layers over the first plurality of dielectric layers. A metal inductor includes a first metal portion, a second metal portion, a third metal portion, and a fourth metal portion, wherein each of the first, the second, the third, and the fourth metal portions extends into the first and the second plurality of dielectric layers. A first metal bridge connects the first metal portion to the second metal portion, wherein the first metal bridge extends into the first plurality of dielectric layers and not into the second plurality of dielectric layers. A second metal bridge connects the third metal portion to the fourth metal portion, wherein the second metal bridge extends into the second plurality of dielectric layers and not into the first plurality of dielectric layers.

    Abstract translation: 一种器件包括在衬底上的第一多个电介质层和在第一多个电介质层上的第二多个电介质层。 金属电感器包括第一金属部分，第二金属部分，第三金属部分和第四金属部分，其中第一，第二，第三和第四金属部分中的每一个延伸到第一和第二金属部分 的介电层。 第一金属桥将第一金属部分连接到第二金属部分，其中第一金属桥延伸到第一多个电介质层中，而不延伸到第二多个电介质层中。 第二金属桥将第三金属部分连接到第四金属部分，其中第二金属桥延伸到第二多个介电层中，而不延伸到第一多个电介质层中。

    ESD block isolation by RF choke
    9.
    发明授权
    ESD block isolation by RF choke 有权
    ESD阻隔隔离ESD

    公开(公告)号：US08958185B2

    公开(公告)日：2015-02-17

    申请号：US13029240

    申请日：2011-02-17

    Applicant: Ming Hsien Tsai ,  Jun-De Jin ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

    Inventor： Ming Hsien Tsai ,  Jun-De Jin ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh

    IPC: H02H9/00 ,  H01L27/02 ,  H02H9/04 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

    CPC classification number: H01L27/0288 ,  H02H9/046

    Abstract: A circuit includes a first node configured to receive a radio frequency (“RF”) signal, a first electrostatic discharge (ESD) protection circuit coupled to a first voltage supply rail for an RF circuit and to a second node, and a second ESD protection circuit coupled to the second node and to a second voltage supply node for the RF circuit. An RF choke circuit is coupled to the second node and to a third node disposed between the first node and the RF circuit.

    Abstract translation: 电路包括被配置为接收射频（“RF”）信号的第一节点，耦合到用于RF电路的第一电压供电轨和第二节点的第一静电放电（ESD）保护电路，以及第二ESD保护 耦合到第二节点的电路和用于RF电路的第二电压供应节点。 RF扼流电路耦合到第二节点和设置在第一节点和RF电路之间的第三节点。

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