公开(公告)号：US09245895B2

公开(公告)日：2016-01-26

申请号：US13190565

申请日：2011-07-26

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US08642441B1

公开(公告)日：2014-02-04

申请号：US11639667

申请日：2006-12-15

申请人： Tim Thurgate ,  Shenqing Fang ,  Kuo-Tung Chang ,  YouSeok Suh ,  Meng Ding ,  Hidehiko Shiraiwa ,  Amol Joshi ,  Harpreet Sachar ,  David Matsumoto ,  Lovejeet Singh ,  Chih-Yuh Yang

发明人： Tim Thurgate ,  Shenqing Fang ,  Kuo-Tung Chang ,  YouSeok Suh ,  Meng Ding ,  Hidehiko Shiraiwa ,  Amol Joshi ,  Harpreet Sachar ,  David Matsumoto ,  Lovejeet Singh ,  Chih-Yuh Yang

IPC分类号： H01L21/76

CPC分类号： H01L27/11563 ,  H01L21/28282 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/11568 ,  H01L29/66833

摘要： A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

摘要翻译： 公开了一种用于制造具有自对准陷阱层和圆形有源区域拐角的存储器件的方法。 在本发明中，在形成电荷捕获层和顶层之前进行STI工艺。 STI过程之后立即暴露有源区域的尖角。 因为这些尖角在这个时候被曝光，所以它们可以通过任何数量的已知的四舍五入技术进行四舍五入。 四舍五入改善了存储设备的性能特征。 在舍入处理之后，电荷捕获结构和其它层可以通过自对准工艺形成。

公开(公告)号：US06773998B1

公开(公告)日：2004-08-10

申请号：US10445129

申请日：2003-05-20

申请人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

发明人： Philip A. Fisher ,  Marina V. Plat ,  Chih-Yuh Yang ,  Christopher F. Lyons ,  Scott A. Bell ,  Douglas J. Bonser ,  Lu You ,  Srikanteswara Dakshina-Murthy

IPC分类号： H01L21336

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/3146 ,  H01L21/32137 ,  H01L21/32139

摘要： A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

摘要翻译： 集成电路的方法包括使用无定形碳ARC掩模。 一层非晶碳材料沉积在导电材料层上方，并且一层抗反射涂层（ARC）材料沉积在无定形碳材料层上。 蚀刻无定形碳材料层和ARC材料层以形成包含ARC材料部分和无定形碳部分的掩模。 然后可以通过根据掩模蚀刻导电材料层而在导电材料层中形成特征。

公开(公告)号：US06451647B1

公开(公告)日：2002-09-17

申请号：US10100819

申请日：2002-03-18

申请人： Chih-Yuh Yang ,  Minh Van Ngo

发明人： Chih-Yuh Yang ,  Minh Van Ngo

IPC分类号： H01L218242

CPC分类号： H01L21/28194 ,  H01L21/2807 ,  H01L21/28123 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/517

摘要： The present invention relates to a process of fabricating a semiconductor device, including steps of providing a first semiconductor wafer; depositing on the first semiconductor wafer a layer comprising a high-K dielectric material layer; depositing on the layer comprising a high-K dielectric material a polysilicon or polysilicon-germanium layer; and forming a gate stack by plasma etching both a portion of the polysilicon or polysilicon-germanium layer and a portion of the layer comprising a high-K dielectric material in a single chamber. In one embodiment, the step of plasma etching is carried out without moving the first wafer from the chamber. In another embodiment an unwanted residual high-K dielectric material is removed by applying a low power plasma treatment.

摘要翻译： 本发明涉及制造半导体器件的方法，包括提供第一半导体晶片的步骤; 在第一半导体晶片上沉积包含高K电介质材料层的层; 在包括高K电介质材料的层上沉积多晶硅或多晶硅 - 锗层; 以及通过在单个室中等离子体蚀刻多晶硅或多晶硅 - 锗层的一部分和包含高K电介质材料的层的一部分来形成栅叠层。 在一个实施例中，在不从腔室移动第一晶片的情况下执行等离子体蚀刻的步骤。 在另一个实施例中，通过施加低功率等离子体处理来去除不想要的残余高K电介质材料。

公开(公告)号：US6133129A

公开(公告)日：2000-10-17

申请号：US306875

申请日：1999-05-07

申请人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott A. Bell ,  Chih-Yuh Yang

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/28123 ,  H01L21/28079 ,  H01L21/321 ,  H01L29/66575 ,  Y10S438/947

摘要： A metal structure is fabricated with a reduced length that is beyond that achievable from photolithography by using a silicidation anneal to control the reduced length. Generally, the present invention includes a step of forming a base metal structure on a semiconductor substrate. The base metal structure has a first predetermined length defined by sidewalls on ends of the first predetermined length of the base metal structure. The present invention also includes the step of depositing a layer of silicon on the sidewalls of the base metal structure, and this layer of silicon has a predetermined thickness. The layer of silicon reacts with the base metal structure at the sidewalls of the base metal structure in a silicidation anneal to form metal silicide comprised of the layer of silicon that has reacted with the base metal structure at the sidewalls of the base metal structure. The base metal structure has a second predetermined length that is reduced from the first predetermined length when the layer of silicon has consumed into the sidewalls of the base metal structure after the silicidation anneal. The second predetermined length depends on the predetermined thickness of the layer of silicon deposited on the sidewalls of the base metal structure before the silicidation anneal. After the silicidation anneal, the metal silicide is then removed from the sidewalls of the base metal structure. A remaining portion of the base metal structure, after the metal silicide is removed, forms the metal structure of the present invention having the reduced length that is substantially equal to the second predetermined length. The present invention may be used to particular advantage when the metal structure having the reduced length forms a gate electrode of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

摘要翻译： 通过使用硅化退火来控制缩短的长度，制造出具有减小的长度的金属结构，其超过了通过光刻可以实现的结构。 通常，本发明包括在半导体衬底上形成贱金属结构的步骤。 贱金属结构具有由基体金属结构的第一预定长度的端部上的侧壁限定的第一预定长度。 本发明还包括在基底金属结构的侧壁上沉积硅层的步骤，并且该硅层具有预定的厚度。 硅层在贱金属结构的侧壁处与基体金属结构反应，以在硅化退火中形成金属硅化物，该金属硅化物由在贱金属结构的侧壁处与基体金属结构反应的硅层组成。 贱金属结构具有第二预定长度，当硅层在硅化退火之后消耗到基体金属结构的侧壁中时，该第一预定长度从第一预定长度减小。 第二预定长度取决于在硅化退火之前沉积在贱金属结构的侧壁上的硅层的预定厚度。 在硅化退火之后，然后从基体金属结构的侧壁去除金属硅化物。 在金属硅化物被除去之后，母体金属结构的剩余部分形成具有基本上等于第二预定长度的减小的长度的本发明的金属结构。 当具有减小的长度的金属结构形成MOSFET（金属氧化物半导体场效应晶体管）的栅电极时，本发明可以被用于特别的优点。

公开(公告)号：US6107172A

公开(公告)日：2000-08-22

申请号：US905104

申请日：1997-08-01

申请人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

发明人： Chih-Yuh Yang ,  Scott A. Bell ,  Daniel Steckert

IPC分类号： H01L21/3213 ,  H01L21/3205 ,  H01L21/302 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/32139 ,  Y10S438/951 ,  Y10S438/952

摘要： A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.

摘要翻译： 通过产生晶片堆叠形成栅极，该晶片堆叠包括在衬底层上的栅极导电层，在导电层上方沉积SiOxNy层以充当底部抗反射涂层（BARC），并在SiO x N y上形成抗蚀剂掩模 层。 接下来，抗蚀剂掩模被各向同性地蚀刻以进一步减小在其中形成的栅极图案的临界尺寸，然后蚀刻下面的BARC和晶片叠层以在导电层外形成栅极。

公开(公告)号：US08012830B2

公开(公告)日：2011-09-06

申请号：US11835542

申请日：2007-08-08

申请人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

发明人： Ning Cheng ,  Kuo-Tung Chang ,  Hiro Kinoshita ,  Chih-Yuh Yang ,  Lei Xue ,  Chungho Lee ,  Minghao Shen ,  Angela Hui ,  Huaqiang Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7887 ,  H01L29/7923

摘要： Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

摘要翻译： 提供了具有改善的TPD特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底上包含两个或更多个存储单元，并且在存储单元之间包含位线电介质的位线开口。 存储单元包含电荷存储层和第一多晶硅栅极。 位线开口延伸到半导体衬底中。 通过将延伸到半导体衬底的位线开口中的位线电介质包含在内，存储器件可以改善存储器单元之间的电隔离，从而防止和/或减轻TPD。

公开(公告)号：US20090152669A1

公开(公告)日：2009-06-18

申请号：US11957737

申请日：2007-12-17

申请人： Lei Xue ,  Aimin Xing ,  Chih-Yuh Yang ,  Angela Hui ,  Chungho Lee

发明人： Lei Xue ,  Aimin Xing ,  Chih-Yuh Yang ,  Angela Hui ,  Chungho Lee

IPC分类号： H01L21/762 ,  H01L23/58

CPC分类号： H01L21/76224 ,  H01L27/10885

摘要： Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.

摘要翻译： 提供了具有改进的BVdss特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底的位线上包含位线电介质; 邻近所述位线电介质的侧表面并在所述半导体衬底的上表面上的第一间隔物; 在所述第一间隔物之间​​的所述半导体衬底中的沟槽; 以及邻近沟槽的侧表面的第二间隔件。 通过在位线之间容纳沟槽和第一和第二间隔物，存储器件可以改善位线之间的电隔离，从而防止和/或减轻位线到位线的电流泄漏并增加BVdss。

公开(公告)号：US06828259B2

公开(公告)日：2004-12-07

申请号：US10017855

申请日：2001-12-14

申请人： Philip A. Fisher ,  Chih-Yuh Yang ,  Marina V. Plat ,  Russell R.A. Callahan ,  Ashok M. Khathuria

发明人： Philip A. Fisher ,  Chih-Yuh Yang ,  Marina V. Plat ,  Russell R.A. Callahan ,  Ashok M. Khathuria

IPC分类号： H01L2126

CPC分类号： H01L21/32139 ,  H01L21/28123

摘要： A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

摘要翻译： 本文公开了一种形成栅极宽度小于70nm的晶体管的工艺。 该工艺包括在光致抗蚀剂层上图案化的栅极的电子束照射，修整在光致抗蚀剂层上图案化的栅极，以及将在光致抗蚀剂层上图案化的栅极蚀刻到设置在光致抗蚀剂层下方的多晶硅层。

公开(公告)号：US06214683B1

公开(公告)日：2001-04-10

申请号：US09290555

申请日：1999-04-12

申请人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

发明人： Qi Xiang ,  Scott Allan Bell ,  Chih-Yuh Yang

IPC分类号： H01L21336

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L29/665

摘要： A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a lateral oxidation process to reduce the lateral dimension of the hard-mask. The lateral oxidation is carried out by selectively oxidizing an oxidizable layer situated between an etch-stop layer and an oxidation resistant layer. Upon completion of the lateral oxidation process, etch-stop layer and the oxidation resistant are removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

摘要翻译： 制造半导体器件的方法包括使用光刻技术形成硬掩膜，然后进行横向氧化处理以减小硬掩模的横向尺寸。 侧向氧化通过选择性地氧化位于蚀刻停止层和抗氧化层之间的可氧化层来进行。 在完成横向氧化工艺后，去除蚀刻停止层和耐氧化层，然后使用剩余的可氧化材料层作为用于形成器件部件的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。