公开(公告)号：US20100013062A1

公开(公告)日：2010-01-21

申请号：US12244295

申请日：2008-10-02

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

摘要： A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

摘要翻译： 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US07576381B2

公开(公告)日：2009-08-18

申请号：US11955397

申请日：2007-12-13

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

摘要翻译： 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US20090061581A1

公开(公告)日：2009-03-05

申请号：US11945199

申请日：2007-11-26

申请人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A method for manufacturing a non-volatile memory is provided. An isolation structure is formed in a trench formed in a substrate. A portion of the isolation structure is removed to form a recess. A first dielectric layer and a first conductive layer are formed sequentially on the substrate. Bar-shaped cap layers are formed on the substrate. The first conductive layer not covered by the bar-shaped cap layers is removed to form first gate structures. A second dielectric layer is formed on the sidewalls of the first gate structures. A third dielectric layer is formed on the substrate between the first gate structures. A second conductive layer is formed on the third dielectric layer. The bar-shaped cap layers and a portion of the first conductive layer are removed to form second gate structures. A doped region is formed in the substrate at two sides of each of the second gate structures.

摘要翻译： 提供一种用于制造非易失性存储器的方法。 在衬底中形成的沟槽中形成隔离结构。 去除隔离结构的一部分以形成凹部。 在基板上依次形成第一介电层和第一导电层。 在基板上形成棒状盖层。 未被棒状帽层覆盖的第一导电层被去除以形成第一栅极结构。 在第一栅极结构的侧壁上形成第二介电层。 在第一栅极结构之间的衬底上形成第三电介质层。 在第三电介质层上形成第二导电层。 条形盖层和第一导电层的一部分被去除以形成第二栅极结构。 在每个第二栅极结构的两侧在衬底中形成掺杂区域。

公开(公告)号：US20090014773A1

公开(公告)日：2009-01-15

申请号：US11946868

申请日：2007-11-29

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7881 ,  H01L29/66825

摘要： A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

摘要翻译： 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20080305593A1

公开(公告)日：2008-12-11

申请号：US11949786

申请日：2007-12-04

申请人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

发明人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

摘要翻译： 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US20080283897A1

公开(公告)日：2008-11-20

申请号：US11857978

申请日：2007-09-19

申请人： Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Yu-Sheng Ding ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/4933 ,  H01L29/66545 ,  H01L29/7887

摘要： The invention provides a flash memory device and a method for fabricating thereof. The device comprises a gate stack layer of a gate dielectric layer and a gate polysilicon layer formed on a substrate, a stack layer comprising a floating polysilicon layer and gate spacer formed on the sidewall of the gate stack layer. A metal layer is formed on the gate stack layer and is utilized in place of a portion of the gate polysilicon layer. Because the metal layer has relatively high conductivity and is electrically connected to a metal plug later formed, current velocity of the device is increased to improve performance.

摘要翻译： 本发明提供一种闪存器件及其制造方法。 该器件包括形成在衬底上的栅极电介质层和栅极多晶硅层的栅极堆叠层，包括形成在栅极堆叠层的侧壁上的浮置多晶硅层和栅极间隔区的堆叠层。 在栅叠层上形成金属层，代替栅极多晶硅层的一部分。 因为金属层具有较高的导电性并且电连接到稍后形成的金属塞上，因此提高了器件的电流速度以提高性能。

公开(公告)号：US20080265302A1

公开(公告)日：2008-10-30

申请号：US11955397

申请日：2007-12-13

申请人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

发明人： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/42336

摘要： A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

摘要翻译： 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06916715B2

公开(公告)日：2005-07-12

申请号：US10694155

申请日：2003-10-27

申请人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

发明人： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L27/148

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

摘要翻译： 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。

公开(公告)号：US06403483B1

公开(公告)日：2002-06-11

申请号：US09695144

申请日：2000-10-25

申请人： Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

发明人： Chung-Peng Hao ,  Chung-Lin Huang ,  Chung-Yuan Lee ,  Yih-Ren Shao ,  Pei-Ing Lee

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/76224

摘要： A shallow trench isolation having an etching stop layer and its method of fabrication. The method utilizes a shield layer such as a silicon nitride layer to serve as an etching stop layer. The etching stop layer is formed in the top position of the shallow trench isolation.

摘要翻译： 具有蚀刻停止层的浅沟槽隔离及其制造方法。 该方法利用诸如氮化硅层的屏蔽层作为蚀刻停止层。 蚀刻停止层形成在浅沟槽隔离的顶部位置。