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    Asymmetrical memory cells and memories using the cells
    31.
    发明申请
    Asymmetrical memory cells and memories using the cells 有权
    不对称存储单元和使用单元的存储器

    公开(公告)号：US20070236982A1

    公开(公告)日：2007-10-11

    申请号：US11392071

    申请日：2006-03-29

    Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    IPC: G11C11/00

    CPC classification number: G11C11/412 ,  H01L27/1104

    Abstract: Techniques are provided for asymmetrical SRAM cells which can be improved, for example, by providing one or more of improved read stability and improved write performance and margin. A first inverter and a second inverter are cross-coupled and configured for selective coupling to true and complementary bit lines under control of read and write word lines. The first inverter is formed by a first, n-type, FET (NFET) and a second, p-type, FET (PFET). Process and/or technology approaches can be employed to adjust the relative strength of the FETS to obtain, for example, read margin, write margin, and/or write performance improvements.

    Abstract translation: 为非对称SRAM单元提供技术，例如可通过提供改进的读取稳定性和改进的写入性能和余量来提供一个或多个。 第一反相器和第二反相器被交叉耦合并且被配置为在读和写字线的控制下选择性地耦合到真和互补的位线。 第一反相器由第一n型FET（NFET）和第二p型FET（PFET）形成。 可以采用过程和/或技术方法来调整FET的相对强度，以获得例如读取余量，写入裕度和/或写入性能改进。

    Independent gate control logic circuitry
    32.
    发明授权
    Independent gate control logic circuitry 失效
    独立门控逻辑电路

    公开(公告)号：US07265589B2

    公开(公告)日：2007-09-04

    申请号：US11168717

    申请日：2005-06-28

    Applicant: Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

    Inventor： Ching-Te Chuang ,  Keunwoo Kim ,  Jente Benedict Kuang ,  Kevin John Nowka

    IPC: H03K19/20 ,  H03K19/094 ,  H03K19/00 ,  H03K19/096

    CPC classification number: H03K19/0963

    Abstract: A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.

    Abstract translation: 动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点 逻辑输入的布尔组合。 逻辑树具有堆叠配置，其具有至少一个多栅极FEAT装置，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点 时钟信号的相位。 多栅极FEAT器件具有耦合到第一逻辑输入的一个栅极和耦合到用于对动态节点预充电的时钟信号的补码的第二栅极。

    Back-gate controlled asymmetrical memory cell and memory using the cell
    33.
    发明申请
    Back-gate controlled asymmetrical memory cell and memory using the cell 有权
    背栅控制的非对称存储单元和使用单元的存储器

    公开(公告)号：US20070201273A1

    公开(公告)日：2007-08-30

    申请号：US11362613

    申请日：2006-02-27

    Applicant: Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    Inventor： Ching-Te Chuang ,  Jae-Joon Kim ,  Keunwoo Kim

    IPC: G11C16/04

    CPC classification number: G11C11/412 ,  G11C11/413

    Abstract: Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.

    Abstract translation: 为非对称存储单元中的背栅极控制提供技术。 在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。 本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。 每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。 每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。 第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

    Cascaded pass-gate test circuit with interposed split-output drive devices
    34.
    发明申请
    Cascaded pass-gate test circuit with interposed split-output drive devices 失效
    带有插入式分离输出驱动装置的级联传输门测试电路

    公开(公告)号：US20070096770A1

    公开(公告)日：2007-05-03

    申请号：US11260571

    申请日：2005-10-27

    Applicant: Ching-Te Chuang ,  Jente Kuang ,  Hung Ngo

    Inventor： Ching-Te Chuang ,  Jente Kuang ,  Hung Ngo

    IPC: H03K19/00

    CPC classification number: G01R31/31725

    Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

    Abstract translation: 包括插入式分离输出驱动装置的级联通过栅极测试电路提供对通孔的临界定时参数的精确测量。 通过通过门的信号的上升时间和下降时间可以在环形振荡器或单稳态延迟线配置中单独测量。 逆变器或其它缓冲电路被提供作为驱动装置来串联耦合通过门。 每个驱动装置中的最终互补树被分开，使得输出下拉晶体管或上拉晶体管中的唯一一个连接到下一个通过栅极输入，而另一个晶体管连接到通过栅极的输出端。 结果是，与连接到通过栅极输入的器件相关联的状态转变在延迟中是主要的，而另一个状态转变直接传播到通过栅极的输出，绕过通过栅极。

    Independently-controlled-gate SRAM
    36.
    发明授权
    Independently-controlled-gate SRAM 有权
    独立控制门SRAM

    公开(公告)号：US08717807B2

    公开(公告)日：2014-05-06

    申请号：US13419291

    申请日：2012-03-13

    Applicant: Ching-Te Chuang ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

    Inventor： Ching-Te Chuang ,  Yin-Nien Chen ,  Chien-Yu Hsieh ,  Ming-Long Fan ,  Pi-Ho Hu ,  Pin Su

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: The present invention provides an IG 7T FinFET SRAM, which adopts independently-controlled-gate super-high-VT FinFETs to achieve a stacking-like property, whereby to eliminate the read disturb and half-select disturb. Further, the present invention uses keeper circuits and read control voltage to reduce leakage current of the bit lines during read. Furthermore, the present invention can effectively overcome the problem of the conventional 6T SRAM that is likely to have read errors at low operation voltage.

    Abstract translation: 本发明提供了一种IG 7T FinFET SRAM，其采用独立控制的栅极超高VT FinFET来实现层叠性质，从而消除读取干扰和半选择干扰。 此外，本发明使用保持器电路和读取控制电压来减少读取期间位线的泄漏电流。 此外，本发明可以有效地克服在低操作电压下可能具有读错误的常规6T SRAM的问题。

    Single-ended SRAM with cross-point data-aware write operation
    37.
    发明授权
    Single-ended SRAM with cross-point data-aware write operation 有权
    具有跨点数据感知写操作的单端SRAM

    公开(公告)号：US08693237B2

    公开(公告)日：2014-04-08

    申请号：US13562330

    申请日：2012-07-31

    Applicant: Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    Inventor： Shyh-Jye Jou ,  Jhih-Yu Lin ,  Ching-Te Chuang ,  Ming-Hsien Tu ,  Yi-Wei Chiu

    IPC: G11C11/00

    CPC classification number: G11C11/412

    Abstract: A single-ended SRAM including at least one memory cell and a third switch is provided. The memory cell includes a data-latching unit, a first switch, a second switch and a data-transferring unit. The data-latching unit is configured for latching the received input data and provides a storage data and the inverse data of the storage data. The first switch transfers a reference data to the data-latching unit according to a first word-line signal. The second switch transfers the reference data to the data-latching unit according to a second word-line signal. The data-transferring unit decides whether or not to transfer the reference data to the bit-line according to the storage data and a control signal. The third switch receives the reference data and the control signal and transfers the reference data to the first switch, the second switch and the data-transferring unit according to the control signal.

    Abstract translation: 提供包括至少一个存储单元和第三开关的单端SRAM。 存储单元包括数据锁存单元，第一开关，第二开关和数据传送单元。 数据锁存单元被配置为锁存接收到的输入数据，并提供存储数据和存储数据的逆数据。 第一开关根据第一字线信号将参考数据传送到数据锁存单元。 第二开关根据第二字线信号将参考数据传送到数据锁存单元。 数据传送单元根据存储数据和控制信号决定是否将参考数据传送到位线。 第三开关接收参考数据和控制信号，并根据控制信号将参考数据传送到第一开关，第二开关和数据传送单元。

    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF
    38.
    发明申请
    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF 有权
    静态随机存取存储器和位线电压控制器

    公开(公告)号：US20140009999A1

    公开(公告)日：2014-01-09

    申请号：US13665941

    申请日：2012-11-01

    Applicant: Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    Inventor： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    IPC: G11C11/00

    CPC classification number: G11C11/413

    Abstract: A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

    Abstract translation: 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

    THRESHOLD VOLTAGE MEASUREMENT DEVICE
    39.
    发明申请
    THRESHOLD VOLTAGE MEASUREMENT DEVICE 有权
    阈值电压测量装置

    公开(公告)号：US20130301343A1

    公开(公告)日：2013-11-14

    申请号：US13597733

    申请日：2012-08-29

    Applicant: Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    Inventor： Ching-Te Chuang ,  Shyh-Jye Jou ,  Geng-Cing Lin ,  Shao-Cheng Wang ,  Yi-Wei Lin ,  Ming-Chien Tsai ,  Wei-Chiang Shih ,  Nan-Chun Lien ,  Kuen-Di Lee ,  Jyun-Kai Chu

    IPC: G11C11/40

    CPC classification number: G11C29/50004 ,  G11C11/41 ,  G11C29/12005

    Abstract: A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

    Abstract translation: 公开了一种阈值电压测量装置。 该器件耦合到6T SRAM。 SRAM包括两个各自耦合到FET的反相器。 一个逆变器的电源端子处于浮动状态; 耦合到逆变器的FET的漏极和源极短路。 两个电压选择器，电阻，放大器和SRAM以负反馈的方式连接。 不同的偏置电压被施加到SRAM，用于测量另一个反相器的两个FET和耦合到另一个反相器的FET的阈值电压。 本发明使用单个电路来测量三个FET的阈值电压，而不改变SRAM的物理结构。 从而加快了测量并降低了制造过程和测量仪器的成本。

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