公开(公告)号：US20130336059A1

公开(公告)日：2013-12-19

申请号：US13527199

申请日：2012-06-19

申请人： Dana Lee ,  Jianmin Huang ,  Mrinal Kochar ,  Ashish Ghai

发明人： Dana Lee ,  Jianmin Huang ,  Mrinal Kochar ,  Ashish Ghai

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/349 ,  G11C29/56008 ,  G11C29/82 ,  G11C2029/4402

摘要： A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.

摘要翻译： 可以使用用于分级块的系统来改善存储器使用。 诸如闪存卡之类的存储器块可以在可以标识每个块的“良好”级别或“坏”级别的滑动标度上分级，而不是二进制好或坏标识。 该分级系统可以利用至少三个等级的等级，其可以通过基于每个块的各个等级更好地利用每个块来提高效率。 块调平分级系统可用于优化最小化产量损失的竞争需求，同时最小化测试缺陷逃逸。

公开(公告)号：US08546214B2

公开(公告)日：2013-10-01

申请号：US12887328

申请日：2010-09-21

申请人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

发明人： Takashi Whitney Orimoto ,  Atsushi Suyama ,  Ming Tian ,  Henry Chin ,  Henry Chien ,  Vinod Robert Purayath ,  Dana Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/28291 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/788

摘要： Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.

摘要翻译： 公开了非电压存储和用于制造非易失性存储器的技术。 在一些实施例中，非易失性存储元件的控制栅极的至少一部分由p型多晶硅形成。 在一个实施例中，控制栅极的下部是p型多晶硅。 控制栅极的上部可以是p型多晶硅，n型多晶硅，金属，金属氮化物等。即使在高Vpgm下，控制栅中的P型多晶硅也可能不会消耗。 因此，如果控制门耗尽，可能会发生的一些问题得到缓解。 例如，具有至少部分p型多晶硅的控制栅极的存储单元可以用比由n型多晶硅形成的存储单元低的Vpgm来编程。

公开(公告)号：US08462547B2

公开(公告)日：2013-06-11

申请号：US12822568

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

公开(公告)号：US08406053B1

公开(公告)日：2013-03-26

申请号：US13239194

申请日：2011-09-21

申请人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

发明人： Deepanshu Dutta ,  Dana Lee ,  Jeffrey Lutze

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

摘要： Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

摘要翻译： 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。

公开(公告)号：US08321727B2

公开(公告)日：2012-11-27

申请号：US12494222

申请日：2009-06-29

申请人： Manuel Antonio D'Abreu ,  Stephen Skala ,  Dana Lee

发明人： Manuel Antonio D'Abreu ,  Stephen Skala ,  Dana Lee

IPC分类号： G11C29/00

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/4402

摘要： Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.

摘要翻译： 公开了响应于存储器的性能参数的变化率的系统和方法。 在特定实施例中，确定非易失性存储器的性能参数的变化率。 将变化率与阈值进行比较，并且响应于确定变化率满足阈值来执行动作。

公开(公告)号：US08094492B2

公开(公告)日：2012-01-10

申请号：US12962902

申请日：2010-12-08

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US20110075477A1

公开(公告)日：2011-03-31

申请号：US12962902

申请日：2010-12-08

申请人： Dana Lee ,  Emilio Yero

发明人： Dana Lee ,  Emilio Yero

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

摘要： A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

摘要翻译： 提出了一种用于编程非易失性存储器的系统，其减少了来自邻居增强的干扰的影响。 存储单元分为两个或更多个组。 在一个示例中，存储器单元被分成奇数和偶数存储器单元; 然而，也可以使用其他组。 在第一触发之前，第一组存储器单元与第二组存储器单元一起编程。 在第一触发之后和在第二触发之前，第一组存储器单元与第二组存储器单元分开编程。 在第二触发之后，第一组存储器单元与第二组存储器单元一起被编程。 在两个触发之前和之后，第一组存储器单元与第二组存储器单元一起被验证。

公开(公告)号：US20100277983A1

公开(公告)日：2010-11-04

申请号：US12835423

申请日：2010-07-13

申请人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

发明人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/107 ,  G11C16/3404 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 存储器单元的子集在擦除之前被预处理。 预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。 作为示例，沿着单个字线的存储器单元可以被预处理。 在预处理之后，使用试写擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US20100261317A1

公开(公告)日：2010-10-14

申请号：US12822568

申请日：2010-06-24

申请人： Jeffrey W. Lutze ,  Dana Lee

发明人： Jeffrey W. Lutze ,  Dana Lee

IPC分类号： H01L21/82 ,  H01L21/336

CPC分类号： H01L27/1158 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11568 ,  H01L27/1157

摘要： A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

公开(公告)号：US20100009503A1

公开(公告)日：2010-01-14

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。