公开(公告)号：US6010957A

公开(公告)日：2000-01-04

申请号：US882423

申请日：1997-06-25

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC分类号： H01L21/76838 ,  H01L23/5283 ,  H01L2924/0002

摘要： A semiconductor device and fabrication process in which tapered conductive lines are formed. Consistent with one embodiment of the invention, a semiconductor device is formed by forming at least one conductive structure over a substrate and forming an insulating layer over the conductive structure. The insulating layer is provided with one or more tapered grooves separated from the conductive structure by a portion of the insulating layer. In each tapered groove a conductive line is formed. The conductive lines may, for example, be metal lines. The conductive structures may, for example, be active regions of a transistor or a previously formed conductive line. A portion of the insulating layer between the conductive layers may be a low dielectric material.

摘要翻译： 形成锥形导电线的半导体器件和制造工艺。 根据本发明的一个实施例，通过在衬底上形成至少一个导电结构并在导电结构上形成绝缘层来形成半导体器件。 绝缘层设置有通过绝缘层的一部分与导电结构分离的一个或多个锥形槽。 在每个锥形槽中形成导线。 导线例如可以是金属线。 导电结构可以例如是晶体管的有源区或者预先形成的导电线。 导电层之间的绝缘层的一部分可以是低电介质材料。

公开(公告)号：US6004849A

公开(公告)日：1999-12-21

申请号：US911745

申请日：1997-08-15

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66659 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/7835

摘要： A method of making an asymmetrical IGFET is disclosed. The method includes providing a semiconductor substrate with an active region, wherein the active region includes a source region and a drain region, forming a gate insulator on the active region, forming a gate on the gate insulator and over the active region, implanting arsenic into the active region to provide a greater concentration of arsenic in the source region than in the drain region, growing an oxide layer over the active region, wherein the oxide layer has a greater thickness over the source region than over the drain region due to the greater concentration of arsenic in the source region than in the drain region, forming a source in the source region and a drain in the drain region, depositing a refractory metal over the gate, the source, the drain, and the oxide layer, and reacting the refractory metal with the drain without reacting the refractory metal with the source, thereby forming a silicide contact on the drain without forming a silicide contact on the source. Advantageously, the IGFET has low source-drain resistance, shallow channel junctions, and an LDD that reduces hot carrier effects.

摘要翻译： 公开了制造不对称IGFET的方法。 该方法包括提供具有有源区的半导体衬底，其中有源区包括源极区和漏极区，在有源区上形成栅极绝缘体，在栅极绝缘体上并在有源区上方形成栅极，将砷注入 所述有源区域在所述源极区域中提供比在所述源极区域中更大的砷浓度，在所述有源区域上生长氧化物层，其中所述氧化物层在所述源极区域上比在所述漏极区域上的厚度大于所述漏极区域上的厚度 在源极区域中的砷浓度比漏极区域中的砷浓度高，在源极区域形成源极，在漏极区域形成漏极，在栅极，源极，漏极和氧化物层上沉积难熔金属，并使 具有漏极的难熔金属，而不使难熔金属与源极反应，从而在漏极上形成硅化物接触，而不在源上形成硅化物接触。 有利地，IGFET具有低源极 - 漏极电阻，浅沟道结和降低热载流子效应的LDD。

公开(公告)号：US5882959A

公开(公告)日：1999-03-16

申请号：US729810

申请日：1996-10-08

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/00

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  Y10S257/905

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity and capacitance by forming a single gate conductor which is shared by an upper level transistor and a lower level transistor. The shared gate conductor is interposed between a pair of gate dielectrics and each gate dielectric is configured between the single gate conductor and a respective substrate. Thus, the upper level transistor is inverted relative to the lower level transistor. The upper level transistor includes a substrate and junction region formed within and opening of an interlevel dielectric. The opening serves to receive the substrate material, but also to demarcate the formation of a pre-existing gate dielectric prior to substrate deposition. Sharing a single gate conductor among two transistors not only minimizes the overall routing between transistor inputs, but also is particularly attuned to inverter formation.

公开(公告)号：US5854115A

公开(公告)日：1998-12-29

申请号：US979042

申请日：1997-11-26

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  Y10S438/97

摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.

摘要翻译： 提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。 在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。 未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。 因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。 对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。 蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。 结果，多层栅极导体的下部比栅极导体的上部宽。

公开(公告)号：US5834350A

公开(公告)日：1998-11-10

申请号：US873116

申请日：1997-06-11

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0688 ,  H01L21/8221

摘要： A second transistor is formed a spaced distance above a first transistor. An interlevel dielectric is first deposited upon the upper surface of the first semiconductor substrate and the first transistor. A second semiconductor substrate, preferably comprising polysilicon, is then formed into the interlevel dielectric. A second transistor is then formed on the upper surface of the second semiconductor substrate. The second transistor is a spaced distance above the first transistor. The two transistors are a lateral distance apart which is smaller than the distance that can be achieved by conventional fabrication of transistors on the upper surface of the wafer. Transistors are more closely packed which results in an increase in the number of devices produced per wafer.

公开(公告)号：US5677224A

公开(公告)日：1997-10-14

申请号：US711381

申请日：1996-09-03

申请人： Daniel Kadosh ,  Mark I. Gardner

发明人： Daniel Kadosh ,  Mark I. Gardner

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/70

CPC分类号： H01L21/823814 ,  H01L27/0922

摘要： An asymmetrical N-channel IGFET and an asymmetrical P-channel IGFET are disclosed. One or both IGFETs include a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region. Preferably, the heavily doped source region and lightly doped drain region provide channel junctions. Forming a first asymmetrical IGFET includes forming a gate with first and second opposing sidewalls over a first active region, applying a first ion implantation to implant lightly doped source and drain regions into the first active region, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming first and second spacers adjacent to the first and second sidewalls, respectively, and applying a third ion implantation to convert a portion of the heavily doped source region outside the first spacer into an ultra-heavily doped source region without doping a portion of the heavily doped source region beneath the first spacer, and to convert a portion of the lightly doped drain region outside the second spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the second spacer. A second asymmetrical IGFET is formed in a related manner. Advantageously, one or both IGFETs have low source-drain series resistance and reduce hot carrier effects.

摘要翻译： 公开了非对称N沟道IGFET和非对称P沟道IGFET。 一个或两个IGFET包括轻掺杂漏极区，重掺杂源极和漏极区以及超重掺杂源极区。 优选地，重掺杂源极区域和轻掺杂漏极区域提供沟道结。 形成第一不对称IGFET包括在第一有源区上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂源极和漏极区域注入到第一有源区中，施加第二离子注入以将 所述轻掺杂源区分别成为重掺杂源区，而不掺杂所述轻掺杂漏区，分别与所述第一和第二侧壁相邻形成第一和第二间隔区，并施加第三离子注入以转换所述重掺杂源区的一部分 在第一间隔物之外的第一间隔物外部，而不掺杂第一间隔物下面的重掺杂源区的一部分，并将第二间隔区外部的轻掺杂漏极区的一部分转换成重掺杂漏极区，而不掺杂 第二间隔物下面的轻掺杂漏极区的一部分。 以相关的方式形成第二不对称IGFET。 有利地，一个或两个IGFET具有低的源 - 漏串联电阻并且减少热载流子效应。

公开(公告)号：US5654215A

公开(公告)日：1997-08-05

申请号：US713388

申请日：1996-09-13

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Robert Dawson

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Robert Dawson

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/66659 ,  H01L21/823468 ,  H01L29/7835 ,  Y10S438/911

摘要： In the present invention, a method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, a gate insulator and a gate electrode, such as a polysilicon, are formed over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls. A first dopant is implanted into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall. First and second symmetrical spacers are then formed adjacent the first and second sidewalls, respectively. A second dopant is implanted into the semiconductor substrate after forming the symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer. After implanting the second dopant, first and second non-symmetrical spacers are formed adjacent the first and second sidewalls, respectively. A heavy dose of a third dopant is then implanted into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region. In another embodiment, a fourth dopant is implanted into the semiconductor substrate before forming the first and second symmetrical spacers further doping the lightly doped drain region.

摘要翻译： 在本发明中，描述了用于制造非对称LDD-IGFET的方法。 在一个实施例中，栅极绝缘体和诸如多晶硅的栅电极形成在半导体衬底之上，栅电极具有顶表面和相对的第一和第二侧壁。 将第一掺杂剂注入到半导体衬底中以提供基本上与第二侧壁对齐的轻掺杂漏极区。 然后分别在第一和第二侧壁附近形成第一和第二对称间隔物。 在形成对称间隔物之后，将第二掺杂剂注入到半导体衬底中，以提供基本上与第二对称间隔物的外部区域对准的适度轻掺杂的漏区。 在注入第二掺杂剂之后，分别在第一和第二侧壁附近形成第一和第二非对称间隔物。 然后将大量的第三掺杂剂注入到半导体衬底中以提供重掺杂的源极区域和重掺杂的漏极区域。 在另一个实施例中，在形成第一和第二对称间隔物之前将第四掺杂剂注入到半导体衬底中，进一步掺杂轻掺杂漏极区。

公开(公告)号：US08190391B2

公开(公告)日：2012-05-29

申请号：US11692989

申请日：2007-03-29

申请人： Daniel Kadosh ,  Gregory A. Cherry ,  Carl I. Bowen ,  Luis De La Fuente ,  Rajesh Vijayaraghavan

发明人： Daniel Kadosh ,  Gregory A. Cherry ,  Carl I. Bowen ,  Luis De La Fuente ,  Rajesh Vijayaraghavan

IPC分类号： G01R15/00 ,  G01R29/00 ,  G01R31/26 ,  G01N37/00 ,  H01L21/66 ,  G06F19/00

CPC分类号： G01R31/287

摘要： A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.

摘要翻译： 一种方法包括接收与多个管芯相关联的第一组参数。 基于第一组参数来确定与所选择的管芯相关联的第一管芯性能度量。 基于第一组参数来确定与由与选定的管芯相邻的多个管芯组成的组相关联的至少一个邻近管芯性能度量。 基于第一管芯性能度量和邻近管芯性能度量，为所选择的管芯确定第二管芯性能度量。

公开(公告)号：US06172402B2

公开(公告)日：2001-01-09

申请号：US09090466

申请日：1998-06-04

申请人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Mark C. Gilmer ,  Daniel Kadosh

IPC分类号： H01L2701

CPC分类号： H01L21/76237 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0921

摘要： An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination. The transistors and other circuit elements formed in the substrate may be interconnected to form an integrated circuit.

摘要翻译： 集成电路包括形成为包括绝缘穿透区域的多个晶体管。 多个晶体管中的每一个包括形成在基板上的沟道，形成在沟道下方的绝缘穿透区域，形成在与沟道的第一端相邻的绝缘穿透区域上的源极，形成在绝缘穿透区域上的漏极， 沟道的第二端，形成在沟道上方的栅极氧化物和形成在栅极氧化物上方的栅极导体。 绝缘区域也可以形成在衬底中，其具有在形成绝缘穿通区域时形成的蚀刻停止定义。 可以在栅极氧化物和沟道之间形成电压阈值区域，并且可以在沟道附近形成轻掺杂区域。 绝缘穿透区域可以是氧化层，也可以形成在氧化物注入步骤中的衬底内，并形成蚀刻停止。 形成在衬底中的晶体管和其它电路元件可以互连以形成集成电路。

公开(公告)号：US6111298A

公开(公告)日：2000-08-29

申请号：US145010

申请日：1998-09-01

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/76

CPC分类号： H01L29/518 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/823456 ,  H01L21/823828 ,  H01L21/82385 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66598 ,  Y10S438/97

摘要： A process is provided for forming a transistor gate conductor having an etch stop arranged at a depth below its upper surface such that the lateral width of the gate conductor above the etch stop may be exclusively narrowed to provide for reduction of transistor channel length. A masking layer, i.e., photoresist, patterned above the gate conductor is isotropically etched so as to minimize its lateral width prior to etching the gate conductor. Portions of the gate conductor not protected by the photoresist may be etched from above the etch stop to define a new pair of opposed sidewall surfaces for the upper portion of the gate conductor. The lateral width of the upper portion of the gate conductor thus may be reduced to a smaller dimension than that of conventional gate conductors. The gate conductor is subjected to an anisotropic etch in which portions of the gate conductor not protected by the narrowed photoresist are etched down to the etch stop. The presence of the etch stop ensures that substantial portions of the etch stop and underlying portions of the gate conductor are not removed before etching is completely terminated. As a result, a lower portion of the multi-layered gate conductor is wider than an upper portion of the gate conductor.

摘要翻译： 提供了一种用于形成晶体管栅极导体的工艺，该晶体管栅极导体具有布置在其上表面下方的深度处的蚀刻停止，使得蚀刻停止点之上的栅极导体的横向宽度可以专门变窄以提供晶体管沟道长度的减小。 在栅极导体上形成图案的掩模层，即光致抗蚀剂被各向同性蚀刻，以便在蚀刻栅极导体之前将其横向宽度最小化。 未被光致抗蚀剂保护的栅极导体的部分可以从蚀刻停止点的上方蚀刻，以限定用于栅极导体的上部的新的一对相对的侧壁表面。 因此，栅极导体的上部的横向宽度可以减小到比常规栅极导体更小的尺寸。 对栅极导体进行各向异性蚀刻，其中不被变窄的光致抗蚀剂保护的栅极导体的部分被蚀刻到蚀刻停止点。 蚀刻停止的存在确保蚀刻停止的大部分和栅极导体的下面的部分在蚀刻完全终止之前不被去除。 结果，多层栅极导体的下部比栅极导体的上部宽。