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47 条记录 (耗时 0.03 秒)

    Computer diagnostic board that provides system monitoring and permits remote terminal access
    31.
    发明授权
    Computer diagnostic board that provides system monitoring and permits remote terminal access 失效
    提供系统监控并允许远程终端接入的计算机诊断板

    公开(公告)号：US6070253A

    公开(公告)日：2000-05-30

    申请号：US775819

    申请日：1996-12-31

    申请人： Siamak Tavallaei ,  Joseph Peter Miller ,  Paul R. Culley

    发明人： Siamak Tavallaei ,  Joseph Peter Miller ,  Paul R. Culley

    IPC分类号： G06F11/273 ,  H05K10/00 ,  G06F15/173

    CPC分类号： G06F11/2736

    摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The video controller is further used for transmitting screen images to a remote computer system to facilitate system failure analysis. A plurality of system management remote units are provided for coupling to various components and busses within the host computer system. The system management remote units (SMR's) connect to the SMM via serial bus and permit the SMM to automatically monitor activities and operating conditions, including determining the source of interrupts on busses and detecting error conditions.

    摘要翻译： 用于主机服务器系统的系统管理模块（SMM）包括连接到系统管理本地总线的系统管理处理器（SMP）。 系统管理本地总线通过系统管理中心（SMC）连接到系统PCI总线。 SMC包括PCI总线的主要仲裁单元，还包括系统管理本地总线的仲裁器。 SMM包括连接到系统管理本地总线的视频控制器和/或键盘和鼠标控制器，以支持SMM的远程安装。 视频控制器还用于将屏幕图像发送到远程计算机系统以便于系统故障分析。 提供多个系统管理远程单元用于耦合到主计算机系统内的各种组件和总线。 系统管理远程单元（SMR）通过串行总线连接到SMM，并允许SMM自动监控活动和操作条件，包括确定总线上的中断源和检测错误情况。

    Method and apparatus for responding to actuation of a power supply switch for a computing system
    32.
    发明授权
    Method and apparatus for responding to actuation of a power supply switch for a computing system 失效
    用于响应用于计算系统的电源开关的致动的方法和装置

    公开(公告)号：US5918059A

    公开(公告)日：1999-06-29

    申请号：US911648

    申请日：1997-08-15

    申请人： Siamak Tavallaei ,  John S. Lacombe ,  Jeffrey S. Autor ,  Jose A. Santin

    发明人： Siamak Tavallaei ,  John S. Lacombe ,  Jeffrey S. Autor ,  Jose A. Santin

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/26

    摘要： Through a menu driven selection procedure, a user is given options for how a server should respond to an actuation of a power switch. In one option, the power switch is disabled to prevent accidental shut down of the power supply in response to power switch actuation. In another option, the shut down of the power supply follows soon after the expiration of a count down timer which is triggered by power switch actuation. A subsequent actuation of the power switch in this option aborts the count down. In yet another option, the shut down of the power supply follows soon after the completion of a graceful shut down of the server operating system which is triggered by power switch actuation. A subsequent actuation of the power switch in this option causes an immediate shut down of the power supply.

    摘要翻译： 通过菜单驱动选择程序，用户可以选择服务器如何响应电源开关的启动。 在一种选择中，电源开关被禁用，以防止电源响应于电源开关致动而意外关闭。 在另一种选择中，在由功率开关致动触发的倒计时定时器期满之后，电源的关闭不久。 此选项中电源开关的后续启动会中止倒计时。 在另一种选择中，在由电源开关致动触发的服务器操作系统的正常关闭完成之后马上关闭电源。 在此选项中随后启动电源开关可立即关闭电源。

    Lower address line prediction and substitution
    33.
    发明授权
    Lower address line prediction and substitution 失效

    公开(公告)号：US5754825A

    公开(公告)日：1998-05-19

    申请号：US444779

    申请日：1995-05-19

    申请人： Brain S. Hausauer ,  Siamak Tavallaei

    发明人： Brain S. Hausauer ,  Siamak Tavallaei

    IPC分类号： G06F12/02 ,  G06F13/28 ,  G06F9/30 ,  G06F1/04

    CPC分类号： G06F13/28 ,  G06F12/0215

    摘要： An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.

    Apparatus to store data and methods to read memory cells
    34.
    发明授权
    Apparatus to store data and methods to read memory cells 有权
    用于存储读取存储器单元的数据和方法的装置

    公开(公告)号：US09311998B2

    公开(公告)日：2016-04-12

    申请号：US14342431

    申请日：2011-09-02

    申请人： Siamak Tavallaei

    发明人： Siamak Tavallaei

    IPC分类号： G11C11/00 ,  G11C13/00 ,  G11C5/04

    CPC分类号： G11C13/004 ,  G11C5/04 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0073

    摘要： Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a current across the memory cell to read a content of the memory cell. During a subsequent read cycle of the memory cell, a subsequent current is applied across the memory cell in the opposite direction to read the content of the memory cell.

    摘要翻译： 公开了存储用于读取存储器单元的数据和方法的装置。 所公开的示例性方法涉及在存储器单元的读取周期期间，跨过存储器单元施加电流以读取存储器单元的内容。 在存储器单元的随后的读取周期期间，沿相反方向跨越存储器单元施加随后的电流以读取存储器单元的内容。

    MEMORY MODULE BUFFER DATA STORAGE
    35.
    发明申请
    MEMORY MODULE BUFFER DATA STORAGE 审中-公开
    存储器模块缓冲器数据存储

    公开(公告)号：US20140325315A1

    公开(公告)日：2014-10-30

    申请号：US14370962

    申请日：2012-01-31

    申请人： Lidia M Warnes ,  Siamak Tavallaei

    发明人： Lidia M Warnes ,  Siamak Tavallaei

    IPC分类号： G06F11/10 ,  G06F11/20

    CPC分类号： G06F11/1004 ,  G06F11/1008 ,  G06F11/2094 ,  G11C5/04 ,  G11C7/10 ,  G11C29/12 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： A memory module (22, 122, 322, 522) including memory devices (24, 324) comprises a memory module buffer (26, 326, 526) having a spare state input (36) and a buffer memory (28). The memory module buffer (26, 326, 526) stores data in the buffer memory (28), the data being re-created from a portion of at least one of the memory devices (24, 324) determined to include an error.

    摘要翻译： 包括存储器设备（24,324）的存储器模块（22,122,322,522）包括具有备用状态输入（36）和缓冲存储器（28）的存储器模块缓冲器（26,326,526）。 存储器模块缓冲器（26,326,526）将数据存储在缓冲存储器（28）中，从被确定为包括错误的存储器件（24,324）中的至少一个的一部分重新创建数据。

    Lower address line prediction and substitution
    38.
    发明授权
    Lower address line prediction and substitution 失效
    较低的地址线预测和替代

    公开(公告)号：US06438627B1

    公开(公告)日：2002-08-20

    申请号：US09076561

    申请日：1998-05-12

    申请人： Brian S. Hausauer ,  Siamak Tavallaei

    发明人： Brian S. Hausauer ,  Siamak Tavallaei

    IPC分类号： G06F1314

    CPC分类号： G06F13/28 ,  G06F12/0215

    摘要： An apparatus is disclosed for predicting and making available in advance certain information, namely the address signals from an expansion bus, so as to relax the timing requirement of the burst transfer cycle. A decoder responds to the control signals of the expansion bus to detect the start and the end of a burst transfer cycle. The decoder controls a counter, which stores the initial address signals of the expansion bus at the start of the burst transfer cycle and predicts the initial address signals by incrementing the address signals during the burst transfer cycle. A multiplexer couples either the predicted address signal to the multiplexer output during the burst transfer cycle or the address signal of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle. In another aspect of the present invention, the low order address signal of the bus is predicted using a second counter. The output of the second counter is merged into the low order address signal of the bus interface devices to properly index the second word of the burst transfer cycle.

    摘要翻译： 公开了一种用于预测并提供某些信息（即来自扩展总线的地址信号）以便放松突发传送周期的定时要求的装置。 解码器响应扩展总线的控制信号以检测突发传送周期的开始和结束。 解码器控制计数器，该计数器在突发传送周期开始时存储扩展总线的初始地址信号，并通过在突发传送周期期间递增地址信号来预测初始地址信号。 当计算机系统不执行EMB突发传输周期时，多路复用器将突发传送周期期间的预测地址信号与EISA总线的地址信号耦合到多路复用器输出。 在本发明的另一方面，使用第二计数器预测总线的低阶地址信号。 第二计数器的输出被合并到总线接口设备的低位地址信号中，以适当地对突发传送周期的第二个字进行索引。

    System and method for controlling remote console functionality assist logic
    39.
    发明授权
    System and method for controlling remote console functionality assist logic 有权
    用于控制远程控制台功能的系统和方法辅助逻辑

    公开(公告)号：US06385682B1

    公开(公告)日：2002-05-07

    申请号：US09313220

    申请日：1999-05-17

    申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

    发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

    IPC分类号： G06F1516

    CPC分类号： G06F11/2294

    摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving-of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

    摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

    System and method for hiding peripheral devices in a computer system
    40.
    发明授权
    System and method for hiding peripheral devices in a computer system 失效
    用于在计算机系统中隐藏外围设备的系统和方法

    公开(公告)号：US06360291B1

    公开(公告)日：2002-03-19

    申请号：US09241203

    申请日：1999-02-01

    申请人： Siamak Tavallaei

    发明人： Siamak Tavallaei

    IPC分类号： G06F1314

    CPC分类号： G06F13/4027

    摘要： A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

    摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏外围设备的至少一部分的动态设备阻塞机制。 计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线， 以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备。 多个I / O总线信号被提供给器件阻塞模块，用于确定哪个总线主机拥有I / O总线以便启动总线周期。 如果总线周期即将代表主处理器及其OS开始，则与选定的外围设备相关联的使能信号被否定，直到该周期完成。 另一方面，如果由IOP启动总线周期，则在交易持续时间内使能使能信号，否则，该信号保持在否定状态。