公开(公告)号：US20130119516A1

公开(公告)日：2013-05-16

申请号：US13294697

申请日：2011-11-11

申请人： David L. Harame ,  Qizhi Liu

发明人： David L. Harame ,  Qizhi Liu

IPC分类号： H01L21/8224 ,  H01L29/735

CPC分类号： H01L29/735 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/0821 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/16 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/7371

摘要： Lateral PNP bipolar junction transistors, methods for fabricating lateral PNP bipolar junction transistors, and design structures for a lateral PNP bipolar junction transistor. An emitter and a collector of the lateral PNP bipolar junction transistor are comprised of p-type semiconductor material that is formed by a selective epitaxial growth process. The source and drain each directly contact a top surface of a device region used to form the emitter and collector. A base contact may be formed on the top surface and overlies an n-type base defined within the device region. The emitter is laterally separated from the collector by the base contact. Another base contact may be formed in the device region that is separated from the other base contact by the base.

摘要翻译： 横向PNP双极结晶体管，制造横向PNP双极结晶体管的方法，以及横向PNP双极结型晶体管的设计结构。 横向PNP双极结晶体管的发射极和集电极由通过选择性外延生长工艺形成的p型半导体材料组成。 源极和漏极各自直接接触用于形成发射极和集电极的器件区域的顶表面。 基部触点可以形成在顶表面上并且覆盖限定在器件区域内的n型基极。 发射极通过基座触点与收集器横向分开。 另一个基底接触可以形成在由基部与另一个基部接触分离的器件区域中。

公开(公告)号：US20130119505A1

公开(公告)日：2013-05-16

申请号：US13294760

申请日：2011-11-11

申请人： David L. Harame ,  Qizhi Liu ,  Robert M. Rassel

发明人： David L. Harame ,  Qizhi Liu ,  Robert M. Rassel

IPC分类号： H01L29/47 ,  G06F9/45 ,  H01L21/329

CPC分类号： H01L29/0684 ,  H01L27/0766 ,  H01L29/0821 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/872

摘要： Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.

摘要翻译： 肖特基势垒二极管，肖特基势垒二极管的制造方法以及肖特基势垒二极管的设计结构。 用选择性外延生长工艺形成用于肖特基势垒二极管的保护环。 可以使用相同的选择性外延生长工艺同时形成用于肖特基势垒二极管的保护环和与肖特基势垒二极管不同的器件区上的垂直双极结二极管的外部基极。

公开(公告)号：US20130009280A1

公开(公告)日：2013-01-10

申请号：US13177146

申请日：2011-07-06

申请人： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

发明人： Renata Camillo-Castillo ,  Peter B. Gray ,  David L. Harame ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L29/73

CPC分类号： H01L29/73 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/107 ,  H01L29/66272 ,  H01L29/7322

摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

摘要翻译： 用于制造双极结型晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。 双极结晶体管包括在本征基极上的电介质层和通过电介质层至少部分地与本征基极分离的外部基极。 发射极开口延伸穿过外部基极和电介质层。 电介质层相对于发射器开口横向凹入以限定内部基极和外部基极之间的腔。 空腔填充有将外部基极和内在基极物理连接在一起的半导体层。

公开(公告)号：US07253096B2

公开(公告)日：2007-08-07

申请号：US11289915

申请日：2005-11-30

申请人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

发明人： Marwan H. Khater ,  James S. Dunn ,  David L. Harame ,  Alvin J. Joseph ,  Qizhi Liu ,  Francois Pagette ,  Stephen A. St. Onge ,  Andreas D. Stricker

IPC分类号： H01L21/4763

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/732 ,  H01L29/7378

摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.

摘要翻译： 公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。 制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。 然后通过在第一非本征基层上的光刻形成电介质着色焊盘。 接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。 使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。 通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

公开(公告)号：US07173274B2

公开(公告)日：2007-02-06

申请号：US10953378

申请日：2004-09-29

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0339

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

摘要翻译： 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US06399458B1

公开(公告)日：2002-06-04

申请号：US09400676

申请日：1999-09-21

申请人： Douglas D. Coolbaugh ,  David L. Harame

发明人： Douglas D. Coolbaugh ,  David L. Harame

IPC分类号： H01L2120

CPC分类号： H01L21/26513 ,  H01L21/02381 ,  H01L21/02667 ,  H01L21/2022

摘要： A method of forming a diffusion region in a silicon substrate having low-resistance, acceptable defect density, reliability and process control comprising the steps of: (a) subjecting a silicon substrate to a first ion implantation step, said first ion implantation step being conducted under conditions such that a region of amorphized Si is formed in said silicon substrate; (b) subjecting said silicon substrate containing said region of amorphized Si to a second ion implantation step, said second ion implantation step being carried out by implanting a dopant ion into said silicon substrate under conditions such that the peak of implant of said dopant ion is within the region of amorphized Si; and (c) annealing said silicon substrate under conditions such that said region of amorphized Si is re-crystallized thereby forming a diffusion region in said silicon substrate is provided.

公开(公告)号：US08916446B2

公开(公告)日：2014-12-23

申请号：US13294671

申请日：2011-11-11

申请人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

发明人： Renata Camillo-Castillo ,  David L. Harame ,  Qizhi Liu ,  Ramana M. Malladi ,  John J. Pekarik

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66

CPC分类号： H01L29/66303 ,  G06F17/5045 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/735

摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

摘要翻译： 用于制造双极结型晶体管的方法，双极结型晶体管以及用于双极结型晶体管的设计结构。 双极结晶体管可以包括布置在不同的发射极指中的多个发射极。 形成了覆盖双极结型晶体管的非本征基极层并填充相邻发射极之间的间隙的硅化物层。 发射极侧壁上的非导电间隔物使发射体与硅化物层电绝缘。 发射极延伸通过外部基极层和硅化物层与本征基极层接触。 发射器可以在替代型工艺中使用牺牲发射器基座形成。

公开(公告)号：US08841750B2

公开(公告)日：2014-09-23

申请号：US13551971

申请日：2012-07-18

申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/732 ,  H01L29/66 ,  H01L29/73 ,  H01L29/08

CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

公开(公告)号：US20130277804A1

公开(公告)日：2013-10-24

申请号：US13452335

申请日：2012-04-20

申请人： Peng Cheng ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

发明人： Peng Cheng ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

IPC分类号： H01L29/732 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/66287 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/7325

摘要： Methods for fabricating a device structure such as a bipolar junction transistor, device structures for a bipolar junction transistor, and design structures for a bipolar junction transistor. The device structure includes a collector region formed in a substrate, an intrinsic base coextensive with the collector region, an emitter coupled with the intrinsic base, a first isolation region surrounding the collector region, and a second isolation region formed at least partially within the collector region. The first isolation region has a first sidewall and the second isolation region having a second sidewall peripherally inside the first sidewall. A portion of the collector region is disposed between the first sidewall of the first isolation region and the second sidewall of the second isolation region.

摘要翻译： 用于制造诸如双极结型晶体管的器件结构的方法，用于双极结型晶体管的器件结构以及用于双极结型晶体管的设计结构。 器件结构包括形成在衬底中的集电极区域，与集电极区域共同延伸的本征基极，与本征基极耦合的发射极，围绕集电极区域的第一隔离区域和至少部分地形成在集电极区域内的第二隔离区域 地区。 第一隔离区域具有第一侧壁，第二隔离区域在第一侧壁周围具有第二侧壁。 集电极区域的一部分设置在第一隔离区域的第一侧壁和第二隔离区域的第二侧壁之间。

公开(公告)号：US08546230B2

公开(公告)日：2013-10-01

申请号：US13296496

申请日：2011-11-15

申请人： James W. Adkisson ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

发明人： James W. Adkisson ,  David L. Harame ,  Robert K. Leidy ,  Qizhi Liu

IPC分类号： H01L21/331 ,  H01L29/66

CPC分类号： H01L29/732 ,  H01L29/7371

摘要： Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.

摘要翻译： 公开了晶体管（例如双极结型晶体管（BJT）或异质结双极晶体管（HBT））的实施例以及形成具有集电极区域的晶体管的方法，该集电极区域具有用于还原的基极 - 集电极结电容Cbc的受保护的上边缘部分。 在实施例中，集电极区域位于衬底内侧向与沟槽隔离区域相邻的位置。 掩模层覆盖沟槽隔离区域并且进一步横向延伸到收集器区域的边缘部分上。 本征基极层的第一部分位于集电极区域的中心部分的上方，并且本征基极层的第二部分位于掩模层之上。 在处理期间，这些掩模层防止在隔离区域 - 集电极区界面处的沟槽隔离区的上角部形成裂缝，并且进一步限制从随后形成的凸起的外在基极层到集电极区域的掺杂剂扩散。