-
公开(公告)号：US20090210587A1
公开(公告)日：2009-08-20
申请号：US12031897
申请日：2008-02-15
IPC分类号： G06F13/00
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3836
摘要： A method and system for implementing store buffer allocation for variable length store data operations are provided. The method includes receiving a store address request and at least one store data request and stepping through data operations for each of the store data requests and an address range for the store data requests to determine alignment and data steering information used to select a storage buffer destination for the data in the store data requests. The method further includes determining availability of the storage buffer by maintaining a reservation list for each storage buffer, maintaining a count of the number of available entries for each storage buffer, updating the reservation list to reflect a reservation acceptance for designated available entries, and clearing entries upon completion of the processing of store data operations. The method also includes reserving the selected storage buffer when the number of available entries meets or exceeds the number of entries required for the data.
摘要翻译： 提供了一种用于实现可变长度存储数据操作的存储缓冲区分配的方法和系统。 所述方法包括：接收存储地址请求和至少一个存储数据请求，并且逐步地进行存储数据请求中的每一个的数据操作和存储数据请求的地址范围，以确定用于选择存储缓冲目的地的对准和数据指导信息 用于存储数据请求中的数据。 该方法还包括通过维护每个存储缓冲器的预约列表来确定存储缓冲器的可用性，维护每个存储缓冲器的可用条目数的计数，更新预留列表以反映指定的可用条目的预约接受，以及清除 店铺数据处理完成后的条目。 该方法还包括当可用条目的数量满足或超过数据所需的条目数时，保留所选择的存储缓冲器。
-
32.发明授权公开(公告)号：US06865645B1
公开(公告)日：2005-03-08
申请号：US09677527
申请日：2000-10-02
CPC分类号： G06F9/3812 , G06F12/0815 , G06F12/0848
摘要： A method of supporting programs that include instructions that modify subsequent instructions in a multi-processor system with a central processing unit including an execution unit, and instruction unit and a plurality of caches including a separate instruction and operand cache.
摘要翻译： 一种支持包括使用包括执行单元的中央处理单元来修改多处理器系统中的后续指令的指令的程序的方法，以及指令单元和包括单独指令和操作数高速缓存的多个高速缓存。
-
公开(公告)号：US06219758B1
公开(公告)日：2001-04-17
申请号：US09047579
申请日：1998-03-25
申请人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
发明人： Jennifer Almoradie Navarro , Barry Watson Krumm , Chung-Lung Kevin Shum , Pak-kin Mak , Michael Fee
IPC分类号： G06F1200
CPC分类号： G06F12/1054
摘要： A central processor uses virtual addresses to access data via cache logic including a DAT and ART, and the cache logic accesses data in the hierarchical storage subsystem using absolute addresses to access data, a part of the first level of the cache memory includes a translator for virtual or real addresses to absolute addresses. When requests are sent for a data fetch and the requested data are not resident in the first level of cache the request for data is delayed and may be forwarded to a lower level of said hierarchical memory, and a delayed request may result in cancellation of any process during a delayed request that has the ability to send back an exception. A delayed request may be rescinded if the central processor has reached an interruptible stage in its pipeline logic at which point, a false exception is forced clearing all I the wait states while the central processor ignores the false exception. Forcing of an exception occurs during dynamic address translation (DAT) or during access register translation (ART). A request for data signal to the storage subsystem cancellation is settable by the first hierarchical level of cache logic. A false exception signal to the first level cache is settable by the storage subsystem logic.
摘要翻译： 中央处理器使用虚拟地址通过包括DAT和ART的高速缓存逻辑来访问数据，并且高速缓存逻辑使用绝对地址访问分层存储子系统中的数据来访问数据，高速缓冲存储器的第一级的一部分包括用于 虚拟或实际地址到绝对地址。 当请求被发送用于数据提取并且所请求的数据不驻留在高速缓存的第一级时，数据请求被延迟并且可以被转发到所述分层存储器的较低级别，并且延迟的请求可能导致任何 在具有发回异常的能力的延迟请求过程中。 如果中央处理器在其流水线逻辑中达到可中断阶段，则可能会撤销延迟请求，此时在中央处理器忽略错误异常时，强制清除所有I等待状态的错误异常。 动态地址转换（DAT）或访问寄存器转换（ART）期间发生异常的强制。 对存储子系统取消的数据信号的请求可以由高速缓存逻辑的第一层级设置。 存储子系统逻辑可以设置到第一级高速缓存的错误异常信号。
-
公开(公告)号：US09164761B2
公开(公告)日：2015-10-20
申请号：US12033351
申请日：2008-02-19
CPC分类号： G06F9/30032 , G06F9/30101 , G06F9/3879
摘要： A pipelined processor including one or more units having storage locations not directly accessible by software instructions. The processor includes a load-store unit (LSU) in direct communication with the one or more units for accessing the storage locations in response to special instructions. The processor also includes a requesting unit for receiving a special instruction from a requestor and a mechanism for performing a method. The method includes broadcasting storage location information from the special instruction to one or more of the units to determine a corresponding unit having the storage location specified by the special instruction. Execution of the special instruction is initiated at the corresponding unit. If the unit executing the special instruction is not the LSU, the data is sent to the LSU. The data is received from the LSU as a result of the execution of the special instruction. The data is provided to the requester.
摘要翻译： 流水线处理器包括一个或多个单元，其具有不能由软件指令直接访问的存储位置。 处理器包括与一个或多个单元直接通信的加载存储单元（LSU），用于响应于特殊指令访问存储位置。 处理器还包括用于从请求者接收特殊指令的请求单元和用于执行方法的机制。 该方法包括将特定指令中的存储位置信息广播到一个或多个单元，以确定具有由特殊指令指定的存储位置的对应单元。 特殊指令的执行在相应的单位启动。 如果执行特殊指令的单元不是LSU，则将数据发送到LSU。 作为执行特殊指令的结果，从LSU接收数据。 数据被提供给请求者。
-
35.发明授权Microprocessor, method and computer program product for direct page prefetch in millicode capable computer system 有权微处理器，方法和计算机程序产品，用于在具有计算机能力的计算机系统中进行直接页面预取公开(公告)号：US08549255B2
公开(公告)日：2013-10-01
申请号：US12032041
申请日：2008-02-15
申请人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David A. Schroter , Mark S. Farrell , Jennifer Navarro , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F12/00
CPC分类号： G06F9/30047 , G06F12/0862
摘要： A microprocessor equipped to provide hardware initiated prefetching, includes at least one architecture for performing: issuance of a prefetch instruction; writing of a prefetch address into a prefetch fetch address register (PFAR); attempting a prefetch according to the address; detecting one of a cache miss and a cache hit; and if there is a cache miss, then sending a miss request to a next cache level and attempting cache access in a non-busy cycle; and if there is a cache hit, then incrementing the address in the PFAR and completing the prefetch. A method and a computer program product are provided.
摘要翻译： 配备提供硬件发起预取的微处理器包括用于执行：发出预取指令的至少一个架构; 将预取地址写入预取提取地址寄存器（PFAR）; 根据地址尝试预取; 检测缓存未命中和缓存命中之一; 并且如果存在高速缓存未命中，则将错误请求发送到下一个高速缓存级别，并在非繁忙周期中尝试高速缓存访问; 并且如果存在缓存命中，则增加PFAR中的地址并完成预取。 提供了一种方法和计算机程序产品。
-
公开(公告)号：US08285941B2
公开(公告)日：2012-10-09
申请号：US12036476
申请日：2008-02-25
IPC分类号： G06F12/06
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译： 提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。 系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。 系统还包括置信柜台。 该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。 该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。 系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。
-
37.发明授权Method, system and computer program product for storing external device result data 失效用于存储外部设备结果数据的方法，系统和计算机程序产品公开(公告)号：US08250336B2
公开(公告)日：2012-08-21
申请号：US12036695
申请日：2008-02-25
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F9/30043 , G06F9/3824 , G06F9/383 , G06F9/3879
摘要： A method, system, and computer program product for storing result data from an external device. The method includes receiving the result data from the external device, the receiving at a system. The result data is stored into a store data buffer. The store data buffer is utilized by the system to contain store data normally generated by the system. A special store instruction is executed to store the result data into a memory on the system. The special store instruction includes a store address. The executing includes performing an address calculation of the store address based on provided instruction information, and updating a memory location at the store address with contents of the store data buffer utilizing a data path utilized by the system to store data normally generated by the system.
摘要翻译： 一种用于从外部设备存储结果数据的方法，系统和计算机程序产品。 该方法包括从外部设备接收结果数据，在系统接收。 结果数据存储到存储数据缓冲区中。 存储数据缓冲器被系统用于包含通常由系统生成的存储数据。 执行特殊存储指令以将结果数据存储到系统中的存储器中。 特殊商店指令包括商店地址。 所述执行包括基于所提供的指示信息执行所述存储地址的地址计算，以及利用所述系统利用的用于存储由所述系统正常生成的数据的数据路径来更新所述存储数据缓冲器的存储位置。
-
38.发明授权Millicode assist instructions for millicode store access exception checking 有权Millicode帮助指令用于millicode存储访问异常检查公开(公告)号：US08176301B2
公开(公告)日：2012-05-08
申请号：US12031756
申请日：2008-02-15
CPC分类号： G06F9/3017 , G06F9/30003 , G06F9/30043 , G06F9/30101 , G06F9/3824 , G06F9/3861
摘要： Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding instructions. The instructions include a millicode instruction with an operand defining an address to check for a store access exception. In addition, an execution unit for executing the millicode instruction performs a method. The method includes receiving the millicode instruction from the instruction unit subsystem, testing for the store access exception at the address as if the test modifier is set absent an update to the OACR, and outputting a result of the testing for the store access exception.
摘要翻译： 经由操作数访问控制寄存器（OACR）提供Millicode存储访问检查指令，该操作数访问控制寄存器（OACR）包括通信地耦合到指令单元子系统的指令单元子系统，用于获取和解码指令。 该指令包括一个具有操作数的millicode指令，其中定义了一个地址来检查存储访问异常。 另外，用于执行millicode指令的执行单元执行一种方法。 该方法包括从指令单元子系统接收millicode指令，测试地址处的存储访问异常，就好像将测试修饰符设置为不存在对OACR的更新，并输出用于存储访问异常的测试结果。
-
公开(公告)号：US08140951B2
公开(公告)日：2012-03-20
申请号：US12031732
申请日：2008-02-15
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译： 提供了一种用于指令地址奇偶校验比较的方法和系统。 该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。 该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。 该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。
-
40.发明授权Method and apparatus for active software disown of cache line's exlusive rights 有权主动软件的方法和装置取消了缓存行的隐藏权限公开(公告)号：US07966453B2
公开(公告)日：2011-06-21
申请号：US11954374
申请日：2007-12-12
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F3/0614 , G06F3/064 , G06F3/0679 , G06F12/0802 , G06F12/0811 , G06F12/0817 , G06F12/0833 , G06F12/0837 , G06F12/0842 , G06F12/0875 , G06F12/128 , G06F2212/1016 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/6042 , G06F2212/621 , G06F2212/69
摘要： Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.
摘要翻译： 软件向处理系统的硬件指示其对特定高速缓存行的存储修改已完成，并且暂时不进行任何修改。 有了这个指示，处理器通过将其所有权从排他性更新到其自己的高速缓存目录和存储控制器（SC）中的只读（或共享）来主动释放其独占所有权。 通过积极放弃专有权，另一个处理器可以立即被给予所述高速缓存行的独占所有权，而不用等待任何处理器的明确的交叉无效确认。 本发明还描述了提供此支持所需的硬件设计。
-
-
-
-
-
-
-
-
-
搜索结果
82 条记录 (耗时 0.07 秒)
