公开(公告)号：US08971014B2

公开(公告)日：2015-03-03

申请号：US12984731

申请日：2011-01-05

申请人： Wei-Chun Hua ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  Jye-Yen Cheng ,  Hua-Chou Tseng

发明人： Wei-Chun Hua ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  Jye-Yen Cheng ,  Hua-Chou Tseng

IPC分类号： H01G4/228 ,  H01L49/02 ,  H01L23/522

CPC分类号： H01G4/005 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  Y10T29/43 ,  H01L2924/00

摘要： A capacitor structure includes first and second sets of electrodes and a plurality of line plugs. The first set of electrodes has a first electrode and a second electrode formed in a first metallization layer among a plurality of metallization layers, wherein the first electrode and the second electrode are separated by an insulation material. The second set of electrodes has a third electrode and a fourth electrode formed in a second metallization layer among the plurality of metallization layers, wherein the third electrode and the fourth electrode are separated by the insulation material. The line plugs connect the second set of electrodes to the first set of electrodes.

摘要翻译： 电容器结构包括第一和第二组电极和多个线插头。 第一组电极具有形成在多个金属化层中的第一金属化层中的第一电极和第二电极，其中第一电极和第二电极被绝缘材料分开。 第二组电极具有形成在多个金属化层之间的第二金属化层中的第三电极和第四电极，其中第三电极和第四电极被绝缘材料隔开。 线插头将第二组电极连接到第一组电极。

公开(公告)号：US08765600B2

公开(公告)日：2014-07-01

申请号：US12913982

申请日：2010-10-28

申请人： Chung-Long Chang ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Hua-Chao Tseng ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

发明人： Chung-Long Chang ,  Chih-Ping Chao ,  Chun-Hung Chen ,  Hua-Chao Tseng ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/4763 ,  H01L29/76

CPC分类号： H01L21/76838 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a gate on a substrate with source/drain (S/D) regions adjacent to the gate. A first dielectric layer overlays the gate and the S/D regions, the first dielectric layer having first contact holes over the S/D regions with first contact plugs formed of a first material and the first contact plugs coupled to respective S/D regions. A second dielectric layer overlays the first dielectric layer and the first contact plugs. A second contact hole formed in the first and second dielectric layers is filled with a second contact plug formed of a second material. The second contact plug is coupled to the gate and interconnect structures formed in the second dielectric layer, the interconnect structures coupled to the first contact plugs. The second material is different from the first material, and the second material has an electrical resistance lower than that of the first material.

摘要翻译： 一种具有栅极的半导体器件，具有与栅极相邻的源极/漏极（S / D）区域的衬底。 第一介电层覆盖栅极和S / D区域，第一介电层在S / D区域上具有第一接触孔，第一接触插塞由第一材料形成，第一接触插塞连接到相应的S / D区域。 第二电介质层覆盖第一电介质层和第一接触插塞。 形成在第一和第二电介质层中的第二接触孔填充有由第二材料形成的第二接触插塞。 第二接触插塞耦合到形成在第二介电层中的栅极和互连结构，互连结构耦合到第一接触插塞。 第二材料与第一材料不同，第二材料的电阻低于第一材料的电阻。

公开(公告)号：US20080100989A1

公开(公告)日：2008-05-01

申请号：US11591643

申请日：2006-11-01

申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

IPC分类号： H01G4/38

CPC分类号： H01L27/0805 ,  H01G4/38 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in each column of the capacitor array; the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have. The unit capacitors further include at least one second unit capacitor in each row and in each column of the capacitor array, wherein the at least one second unit is interconnected and evenly distributed throughout the array.

摘要翻译： 集成电路装置包括电容器阵列，其包括以行和列排列的单位电容器，其中每个单位电容器由两个电绝缘电容器板形成。 单位电容器包括电容器阵列的每一行和每列中的至少一个第一单位电容器; 所述至少一个第一单元电容器互连，其中所述电容器阵列的每一行包括与其它行和列具有相同数量的所述至少一个第一单位电容器，并且其中所述电容器阵列的每列包括相同数量的 其他行和列具有至少一个第一单位电容器。 单元电容器还包括在电容器阵列的每一列和每列中的至少一个第二单位电容器，其中该至少一个第二单元互连并均匀分布在整个阵列中。

公开(公告)号：US20080099879A1

公开(公告)日：2008-05-01

申请号：US11591644

申请日：2006-11-01

申请人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

发明人： Chia-Yi Chen ,  Chung-Long Chang ,  Chih-Ping Chao

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first capacitor comprising a plurality of first unit capacitors interconnected to each other, each having a first unit capacitance; and a second capacitor comprising a plurality of second unit capacitors interconnected to each other, each having a second unit capacitance, wherein the first unit capacitors and the second unit capacitors have equal numbers of unit capacitors. The first unit capacitors and the second unit capacitors are arranged in an array with rows and columns and placed in an alternating pattern in each row and each column. The first and the second unit capacitors each have a total number greater than two.

摘要翻译： 半导体器件包括：第一电容器，包括彼此互连的多个第一单位电容器，每个具有第一单位电容; 以及包括彼此互连的多个第二单位电容器的第二电容器，每个具有第二单位电容，其中所述第一单位电容器和所述第二单位电容器具有相等数目的单位电容器。 第一单元电容器和第二单元电容器以具有行和列的阵列排列并且以每行和每列置于交替图案中。 第一和第二单元电容器的总数大于2。

公开(公告)号：US20070158783A1

公开(公告)日：2007-07-12

申请号：US11328502

申请日：2006-01-09

申请人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

发明人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.

摘要翻译： 用于集成电路的改进的互指电容结构的系统和方法。 优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。 第一介电层沉积在第一层条带的每条上。 基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。 通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。 基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

公开(公告)号：US09620421B2

公开(公告)日：2017-04-11

申请号：US12948184

申请日：2010-11-17

申请人： Chien-Chih Ho ,  Chih-Ping Chao ,  Hua-Chou Tseng ,  Chun-Hung Chen ,  Chia-Yi Su ,  Alex Kalnitsky ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

发明人： Chien-Chih Ho ,  Chih-Ping Chao ,  Hua-Chou Tseng ,  Chun-Hung Chen ,  Chia-Yi Su ,  Alex Kalnitsky ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L23/481 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method of forming an integrated circuit structure includes providing a gate strip in an inter-layer dielectric (ILD) layer. The gate strip comprises a metal gate electrode over a high-k gate dielectric. An electrical transmission structure is formed over the gate strip and a conductive strip is formed over the electrical transmission structure. The conductive strip has a width greater than a width of the gate strip. A contact plug is formed above the conductive strip and surrounded by an additional ILD layer.

公开(公告)号：US08169014B2

公开(公告)日：2012-05-01

申请号：US11328502

申请日：2006-01-09

申请人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

发明人： Yueh-You Chen ,  Chung-Long Chang ,  Chih-Ping Chao

IPC分类号： H01L29/92

CPC分类号： H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： System and method for an improved interdigitated capacitive structure for an integrated circuit. A preferred embodiment comprises a first layer of a sequence of substantially parallel interdigitated strips, each strip of either a first polarity or a second polarity, the sequence alternating between a strip of the first polarity and a strip of the second polarity. A first dielectric layer is deposited over each strip of the first layer of strips. A first extension layer of a sequence of substantially interdigitated extension strips is deposited over the first dielectric layer, each extension strip deposited over a strip of the first layer of the opposite polarity. A first sequence of vias is coupled to the first extension layer, each via deposited over an extension strip of the same polarity. A second layer of a sequence of substantially parallel interdigitated strips can be coupled to the first sequence of vias.

摘要翻译： 用于集成电路的改进的互指电容结构的系统和方法。 优选实施例包括基本上平行的叉指序列序列的第一层，每个条带具有第一极性或第二极性，该序列在第一极性的条带和第二极性的条之间交替。 第一介电层沉积在第一层条带的每条上。 基本上交错的延伸条的序列的第一延伸层沉积在第一介电层上，每个延伸条沉积在具有相反极性的第一层的条上。 通孔的第一序列耦合到第一延伸层，每个通孔沉积在相同极性的延伸条上。 基本上平行的叉指序列序列的第二层可以耦合到第一序列通孔。

公开(公告)号：US07968968B2

公开(公告)日：2011-06-28

申请号：US12790526

申请日：2010-05-28

申请人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

发明人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

IPC分类号： H01L27/08

CPC分类号： H01L28/10

摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.

摘要翻译： 一种利用垫金属层的电感器。 电感器包括金属螺旋，金属桥和金属互连。 金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。 金属互连连接到金属桥的另一端。 此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

公开(公告)号：US20100265025A1

公开(公告)日：2010-10-21

申请号：US12790526

申请日：2010-05-28

申请人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

发明人： Sung-Hsiung Wang ,  Chih-Ping Chao ,  Chia-Yu Su

IPC分类号： H01F5/00

CPC分类号： H01L28/10

摘要： An inductor utilizing a pad metal layer. The inductor comprises a metal spiral, a metal bridge, and a metal interconnect. The metal bridge is formed with the pad metal layer and a plurality of vias and has one end connected to the metal spiral. The metal interconnect is connected to the other end of the metal bridge. In addition, resistivity of the pad metal layer is lower than that of the metal spiral.

摘要翻译： 一种利用垫金属层的电感器。 电感器包括金属螺旋，金属桥和金属互连。 金属桥形成有焊盘金属层和多个通孔，并且一端连接到金属螺旋。 金属互连连接到金属桥的另一端。 此外，焊垫金属层的电阻率低于金属螺旋的电阻率。

公开(公告)号：US07718494B2

公开(公告)日：2010-05-18

申请号：US11784721

申请日：2007-04-09

申请人： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

发明人： Yung Chih Tsai ,  Michael Yu ,  Chih-Ping Chao ,  Chih-Sheng Chang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823892 ,  H01L21/823412 ,  H01L21/823493 ,  H01L21/823807 ,  Y10S438/919

摘要： A method for forming a high-voltage drain metal-oxide-semiconductor (HVD-MOS) device includes providing a semiconductor substrate; forming a well region of a first conductivity type; and forming an embedded well region in the semiconductor substrate and only on a drain side of the HVD-MOS device, wherein the embedded region is of a second conductivity type opposite the first conductivity type. The step of forming the embedded well region includes simultaneously doping the embedded well region and a well region of a core regular MOS device, and simultaneously doping the embedded well region and a well region of an I/O regular MOS device, wherein the core and I/O regular MOS devices are of the first conductivity type. The method further includes forming a gate stack extending from over the embedded well region to over the well region.

摘要翻译： 一种用于形成高电压漏极金属氧化物半导体（HVD-MOS）器件的方法包括：提供半导体衬底; 形成第一导电类型的阱区; 以及在所述半导体衬底中并且仅在所述HVD-MOS器件的漏极侧上形成嵌入阱区域，其中所述嵌入区域是与所述第一导电类型相反的第二导电类型。 形成嵌入阱区的步骤包括同时掺杂嵌入阱区和芯规则MOS器件的阱区，并同时掺杂I / O规则MOS器件的嵌入阱区和阱区，其中核和 I / O常规MOS器件是第一导电类型。 所述方法还包括形成从所述嵌入阱区域上方延伸到所述阱区域的栅极堆叠。