公开(公告)号：US06783695B1

公开(公告)日：2004-08-31

申请号：US09643946

申请日：2000-08-23

Applicant: Kevin J. Torek ,  Donald L. Yates

Inventor： Kevin J. Torek ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/02071 ,  G03F7/423 ,  G03F7/426 ,  H01L21/02063

Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of a fluorine source, a non-aqueous solvent, a complementary acid, and a surface passivation agent. The fluorine source is typically hydrofluoric acid. The non-aqueous solvent is typically a polyhydric alcohol such as propylene glycol. The complementary acid is typically either phosphoric acid or hydrochloric acid. The surface passivation agent is typically a carboxylic acid such as citric acid. Exposing the substrate to the conditioning solution removes the remaining dry etch residues while minimizing removal of material from desired substrate features.

Abstract translation: 从半导体衬底干法蚀刻工艺后残留的有机金属和有机硅酸盐残渣的方法。 将基材暴露于氟源，非水溶剂，互补酸和表面钝化剂的调理溶液中。 氟源通常是氢氟酸。 非水溶剂通常是多元醇如丙二醇。 互补酸通常是磷酸或盐酸。 表面钝化剂通常是羧酸如柠檬酸。 将基材暴露于调理溶液中，除去剩余的干蚀刻残留物，同时最小化从所需基材特征中去除材料。

公开(公告)号：US06673675B2

公开(公告)日：2004-01-06

申请号：US10119952

申请日：2002-04-11

Applicant: Donald L. Yates ,  Garry A. Mercaldi

Inventor： Donald L. Yates ,  Garry A. Mercaldi

IPC: H01L21336

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor is provided in a trench in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a first dielectric layer is deposited over the first conductor and insulating layer to a thickness at least greater than the thickness of a desired MRAM cell. The first dielectric layer is then patterned and etched to form an opening over the first conductor for the cell shapes. Then, the magnetic layers comprising the MRAM cell are consecutively formed within the cell shapes and the first dielectric layer.

Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 第一导体设置在绝缘层中的沟槽中，并且绝缘层的上表面和第一导体被平坦化。 然后，将第一介电层沉积在第一导体和绝缘层上方至少大于所需MRAM单元厚度的厚度。 然后对第一介电层进行图案化和蚀刻，以在单元形状的第一导体上形成开口。 然后，包含MRAM单元的磁性层在单元格形状和第一介电层内连续地形成。

公开(公告)号：US06656289B2

公开(公告)日：2003-12-02

申请号：US09943844

申请日：2001-08-30

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B700

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.

公开(公告)号：US06517738B1

公开(公告)日：2003-02-11

申请号：US09632088

申请日：2000-08-02

Applicant: Kevin J. Torek ,  Donald L. Yates

Inventor： Kevin J. Torek ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/31116 ,  C09K13/08 ,  C11D7/08 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/31144

Abstract: A method for removing organometallic and organosihicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.

Abstract translation: 一种从半导体衬底干法蚀刻工艺后残留的有机金属和有机物残留物的方法。 将基底暴露于磷酸，氢氟酸和羧酸（例如乙酸）的调理溶液中，其除去剩余的干蚀刻残留物，同时最小化从所需底物特征中去除材料。 调理溶液的大致比例通常为80至95％的乙酸，1至15％的磷酸和0.01至5.0％的氢氟酸。

公开(公告)号：US08492288B2

公开(公告)日：2013-07-23

申请号：US12136661

申请日：2008-06-10

Applicant: Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  B08B3/00

CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

公开(公告)号：US07482176B2

公开(公告)日：2009-01-27

申请号：US11705211

申请日：2007-02-12

Applicant: Donald L. Yates ,  Karen T Signorini

Inventor： Donald L. Yates ,  Karen T Signorini

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L21/32139 ,  H01L43/12

Abstract: A method for forming an MRAM bit is described that includes providing a covering layer over an integrated circuit structure. In one embodiment, the covering layer includes tantalum. A first mask layer is formed over the covering layer followed by a second mask layer. The first mask layer and second mask layer are etchable by the same etching process. The first and second mask layer are etched. Etch residue is removed from the first and second mask layers. The first mask layer is then selectively removed and the second mask layer remains.

Abstract translation: 描述了一种用于形成MRAM位的方法，其包括在集成电路结构上提供覆盖层。 在一个实施例中，覆盖层包括钽。 第一掩模层形成在覆盖层之后，随后是第二掩模层。 第一掩模层和第二掩模层可以通过相同的蚀刻工艺进行蚀刻。 蚀刻第一和第二掩模层。 蚀刻残渣从第一和第二掩模层去除。 然后选择性地去除第一掩模层，并且残留第二掩模层。

公开(公告)号：US07422639B2

公开(公告)日：2008-09-09

申请号：US11188048

申请日：2005-07-22

Applicant: Donald L. Yates

Inventor： Donald L. Yates

IPC: B08B3/04

CPC classification number: H01L21/67034 ,  H01L21/02052 ,  H01L21/02057 ,  H01L21/67028 ,  H01L21/67057 ,  Y10S134/902

Abstract: The present invention relates to a method of cleaning and drying a semiconductor structure in a modified conventional gas etch/rinse or dryer vessel.

Abstract translation: 本发明涉及一种在改进的常规气体蚀刻/漂洗或干燥容器中清洗和干燥半导体结构的方法。

公开(公告)号：US07067466B2

公开(公告)日：2006-06-27

申请号：US10187139

申请日：2002-07-01

Applicant: Donald L. Yates ,  Max F. Hineman

Inventor： Donald L. Yates ,  Max F. Hineman

IPC: C09K13/00

CPC classification number: C11D7/08 ,  C11D7/265 ,  C11D11/0047

Abstract: A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is ascorbic acid or is an organic acid having two or more carboxylic acid groups (e.g., citric acid). The water can be present in about 40 wt. % to about 85 wt. % of the composition, the phosphoric acid can be present in about 0.01 wt. % to about 10 wt. % of the composition, and the organic acid can be present in about 10 wt. % to about 60 wt. % of the composition. The composition can be used for cleaning various surfaces, such as, for example, patterned metal layers and vias by exposing the surfaces to the composition.

公开(公告)号：US06867148B2

公开(公告)日：2005-03-15

申请号：US09858980

申请日：2001-05-16

Applicant: Donald L. Yates ,  Paul A. Morgan

Inventor： Donald L. Yates ,  Paul A. Morgan

IPC: B08B3/08 ,  G03F7/42 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/302

CPC classification number: H01L21/02071 ,  B08B3/08 ,  B08B2203/005 ,  G03F7/423 ,  H01L21/31133

Abstract: Organic acid components are used to increase the solubility of ozone in aqueous solutions for use in removing organic materials, such as polymeric resist and/or post-etch residues, from the surface of an integrated circuit device during fabrication. Each organic acid component is preferably chosen for its metal-passivating effect. Such solutions can have significantly lower corrosion rates when compared to ozonated aqueous solutions using common inorganic acids for ozone solubility enhancement due to the passivating effect of the organic acid component.

Abstract translation: 有机酸组分用于增加臭氧在水溶液中的溶解度，用于在制造期间从集成电路器件的表面去除有机材料，例如聚合物抗蚀剂和/或蚀刻后残留物。 优选选择每种有机酸组分用于其金属钝化作用。 与使用普通无机酸进行臭氧溶解度增强的臭氧化水溶液相比，由于有机酸组分的钝化作用，这种溶液可以具有显着更低的腐蚀速率。

公开(公告)号：US06833084B2

公开(公告)日：2004-12-21

申请号：US09285773

申请日：1999-04-05

Applicant: Garry A. Mercaldi ,  Donald L. Yates

Inventor： Garry A. Mercaldi ,  Donald L. Yates

IPC: C09K1300

CPC classification number: H01L21/32134

Abstract: The present invention provides an etching composition which includes a polyhydric alcohol in combination with two inorganic acids. Preferably the etching composition of the present invention is a mixture of a glycol, nitric acid and hydrofluoric acid, with propylene glycol being preferred. The etching composition of the present invention achieves a selectivity of greater than 70:1, doped material to undoped material. The present invention provides an etching formulation which has increased selectivity of doped polysilicon to undoped polysilicon and provides an efficient integrated circuit fabrication process without requiring time consuming and costly processing modifications to the etching apparatus or production apparatus.

Abstract translation: 本发明提供一种蚀刻组合物，其包含与两种无机酸组合的多元醇。 优选地，本发明的蚀刻组合物是二醇，硝酸和氢氟酸的混合物，优选丙二醇。 本发明的蚀刻组合物实现大于70:1的掺杂材料对未掺杂材料的选择性。 本发明提供了一种蚀刻配方，其具有增加掺杂多晶硅对未掺杂多晶硅的选择性，并且提供了有效的集成电路制造工艺，而不需要对蚀刻设备或生产设备进行耗时且昂贵的处理修改。