利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.033 秒)

    Method of fabricating a ferroelectric memory device
    31.
    发明授权
    Method of fabricating a ferroelectric memory device 有权
    制造铁电存储器件的方法

    公开(公告)号：US06815227B2

    公开(公告)日：2004-11-09

    申请号：US10744378

    申请日：2003-12-22

    申请人： Hyeong-Geun An

    发明人： Hyeong-Geun An

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.

    摘要翻译： 提供了一种铁电存储器件及其制造方法。 铁电存储器件包括至少两个电容器图案和板线。 每个电容器图案包括堆叠在半导体衬底上的下电极，铁电层和上电极。 板线的顶部被氧阻挡层覆盖，并且板状线的侧壁被氧隔离隔离物覆盖。

    Ferroelectric memory device and method of forming the same
    32.
    发明授权
    Ferroelectric memory device and method of forming the same 失效
    铁电存储器件及其形成方法

    公开(公告)号：US06815226B2

    公开(公告)日：2004-11-09

    申请号：US10613102

    申请日：2003-07-07

    申请人： Kyu-Mann Lee ,  Yong-Tak Lee ,  Hyeong-Geun An

    发明人： Kyu-Mann Lee ,  Yong-Tak Lee ,  Hyeong-Geun An

    IPC分类号： H01L2100

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11507 ,  H01L28/57

    摘要： The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.

    摘要翻译： 形成铁电存储器件的方法包括在衬底上形成电容器图案，每个电容器图案具有粘合剂辅助图案，下电极，铁电体图案和上电极。 在衬底上形成氧阻隔层，并且被蚀刻以暴露铁电图案的侧壁，而不是粘合助剂图案的侧壁。 然后，进行用于固化铁电型图案的铁电性的热处理。

    FRAM and method of fabricating the same
    33.
    发明授权
    FRAM and method of fabricating the same 有权
    FRAM及其制造方法

    公开(公告)号：US06686620B2

    公开(公告)日：2004-02-03

    申请号：US10109432

    申请日：2002-03-27

    申请人： Hyeong-Geun An ,  Soon-Oh Park

    发明人： Hyeong-Geun An ,  Soon-Oh Park

    IPC分类号： H01L27108

    CPC分类号： H01L28/65 ,  H01L27/10852 ,  H01L27/10882 ,  H01L28/57

    摘要： A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal. Additionally, the fill layer may be formed of a fill material that has a superior gap fill capability or of a material that has a low stress relationship with respect to the capacitor's top metal.

    摘要翻译： 具有铁电电容器的FRAM包括圆柱形底部电极。 铁电体薄膜层叠在底部电极上，并且顶部电极的第一部分形成在铁电膜上并与其形成共形。 然后，在铁电体膜上的电极的第一部分的侧壁之间留下的空隙填充有用于填充层的填充材料。 然后将填充层的填充材料平坦化以与顶部电极的第一部分的上表面平齐并暴露。 然后，顶部电极的第二部分形成在填充层之上并与暴露的例如电极接触。 电极的第一部分的周边区域。 填充层的填充材料可以由多晶硅，氧化硅或其它材料例如另一种金属形成。 另外，填充层可以由具有优异间隙填充能力的填充材料或与电容器的顶部金属具有低应力关系的材料形成。

    Phase change memory device and method of fabricating the same
    35.
    发明授权
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07767568B2

    公开(公告)日：2010-08-03

    申请号：US11905244

    申请日：2007-09-28

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

    摘要翻译： 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上。

    Methods of forming multi-level cell of semiconductor memory
    36.
    发明申请
    Methods of forming multi-level cell of semiconductor memory 有权
    形成半导体存储器多级单元的方法

    公开(公告)号：US20100093130A1

    公开(公告)日：2010-04-15

    申请号：US12587772

    申请日：2009-10-13

    申请人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    发明人： Gyu-Hwan Oh ,  Hyeong-Geun An ,  Soon-Oh Park ,  Dong-Ho Ahn ,  Young-Lim Park

    IPC分类号： H01L21/06

    CPC分类号： H01L45/141 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/1666 ,  H01L45/1683

    摘要： Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided.

    摘要翻译： 提供了一种形成半导体存储单元的方法，其中为了在存储单元中存储两个或更多个数据，三个或更多个底部电极触点（BEC）和相变材料（GST）在单个存储单元上具有并联结构 接触插头（CP）和设定电阻根据三个或更多个底部电极触点的厚度（S），长度（L）或电阻率（＆rgr）而改变，因此复位电阻和三种不同的设定电阻使数据不能 在设置和复位状态下存储。 此外，形成其中三个或更多个相变材料（GST）在单个底部电极接触上具有平行结构的存储单元的方法，并且相变材料根据组成比或类型具有不同的设定电阻，因此 可以实现四个或更多个不同的电阻。