公开(公告)号：US07312130B2

公开(公告)日：2007-12-25

申请号：US10977385

申请日：2004-10-29

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Byeong-Yun Nam ,  Kyeong-Koo Ghi ,  Eun-Ae Chung ,  Sung-Il Cho

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/91

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract translation: 形成电容器结构的方法可以包括在衬底上形成绝缘层，在绝缘层上形成第一电容器电极，在第一电容器电极的部分上形成电容器电介质层，以及在电容器电介质层上形成第二电容器电极， 电容器介电层位于第一和第二电容器电极之间。 更具体地，第一电容器电极可以在其中限定空腔，其中腔具有相对于衬底平行的第一部分和相对于衬底垂直的第二部分。 还讨论了相关结构。

公开(公告)号：US07183600B2

公开(公告)日：2007-02-27

申请号：US10858727

申请日：2004-06-02

Applicant: Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

Inventor： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Myeong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC: H01L29/76

CPC classification number: H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

Abstract: A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

Abstract translation: 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20070020780A1

公开(公告)日：2007-01-25

申请号：US11370478

申请日：2006-03-07

Applicant: Kye-Hyun Baek ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Yong-Jin Kim

Inventor： Kye-Hyun Baek ,  Chang-Jin Kang ,  Gyung-Jin Min ,  Yong-Jin Kim

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/00

Abstract: In one embodiment, a method of processing a semiconductor substrate includes measuring a state of a processing chamber contamination before processing each semiconductor substrate. A process condition is then changed responsive to the state of chamber contamination to compensate for an influence of the state of chamber contamination on the process condition. If the change in process condition is outside of predetermined margin, a warning may be generated and the process may be stopped.

Abstract translation: 在一个实施例中，处理半导体衬底的方法包括在处理每个半导体衬底之前测量处理室污染的状态。 响应于室污染的状态来改变工艺条件以补偿室污染状态对工艺条件的影响。 如果处理条件的改变超出预定余量，则可能产生警告并且可以停止处理。

公开(公告)号：US20050031995A1

公开(公告)日：2005-02-10

申请号：US10867468

申请日：2004-06-14

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: G03F9/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US06177320B1

公开(公告)日：2001-01-23

申请号：US09226961

申请日：1999-01-08

Applicant: Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

Inventor： Chang-Hyun Cho ,  Hong-Sik Jeong ,  Jae-Goo Lee ,  Chang-Jin Kang ,  Sang-Sup Jeong ,  Chul Jung ,  Chan-Ouk Jung

IPC: H01L21336

CPC classification number: H01L27/10844 ,  H01L21/31144 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76897 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888

Abstract: A self aligned contact pad in a semiconductor device and a method for forming the self aligned contact pad are disclosed. A bit line contact pad and a storage node contact pad are simultaneously formed by using a photoresist layer pattern having a T-shaped opening including at least two contact regions. An etch stopping layer is formed over a semiconductor substrate and over a transistor. An interlayer dielectric layer is then formed over the etch stopping layer. Next, the interlayer dielectric layer is planarized to have a planar top surface. A mask pattern having a T-shaped opening is then formed over the interlayer dielectric layer, exposing the active region and a portion of the inactive region. The interlayer dielectric layer and etch stopping layer are sequentially etched to reveal a top surface of the semiconductor substrate using the mask pattern, thereby forming a self aligned contact opening exposing a top surface of the semiconductor substrate. The mask pattern is then removed. A conductive layer is formed in the self aligned contact opening and over the interlayer dielectric layer. The conductive layer and the interlayer dielectric layer are planarization-etched to reveal a top surface of the gate mask, thereby forming at least two contact pads.

Abstract translation: 公开了半导体器件中的自对准接触焊盘和用于形成自对准接触焊盘的方法。 通过使用具有包括至少两个接触区域的T形开口的光致抗蚀剂层图案，同时形成位线接触焊盘和存储节点接触焊盘。 在半导体衬底上并在晶体管上形成蚀刻停止层。 然后在蚀刻停止层上形成层间电介质层。 接下来，层间绝缘层被平坦化以具有平坦的顶表面。 然后在层间电介质层上形成具有T形开口的掩模图案，暴露有源区和一部分非活性区。 依次蚀刻层间电介质层和蚀刻停止层，以使用掩模图案露出半导体衬底的顶表面，从而形成暴露半导体衬底的顶表面的自对准接触开口。 然后去除掩模图案。 导电层形成在自对准接触开口中以及层间电介质层之上。 对导电层和层间电介质层进行平面蚀刻以露出栅极掩模的顶表面，从而形成至少两个接触焊盘。

公开(公告)号：US08080886B2

公开(公告)日：2011-12-20

申请号：US12111651

申请日：2008-04-29

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: H01L23/544

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US07479445B2

公开(公告)日：2009-01-20

申请号：US11247937

申请日：2005-10-11

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Sung-Hoon Chung

IPC: H01L21/28 ,  H01L21/335

CPC classification number: H01L29/1037 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/76

Abstract: Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

Abstract translation: 形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。 通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。 沟槽填充有栅电极。 第一电绝缘层在含有氧的环境中被图案化。 当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

公开(公告)号：US07384843B2

公开(公告)日：2008-06-10

申请号：US11260377

申请日：2005-10-28

Applicant: Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

Inventor： Dong-Chan Kim ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Seung-Pil Chung

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method of manufacturing a semiconductor memory device comprises forming floating gates on active regions of a semiconductor substrate and forming a capping layer on the floating gates. An isolation layer located in the semiconductor substrate between the floating gates is anisotropically etched using the capping layer as an etch mask to form recessed regions. The recessed regions are formed to have a width smaller than a distance between the floating gates, and bottom surfaces positioned below bottom surfaces of the floating gates. Control gate electrodes are formed across the active regions over the floating gates and the control gate electrodes have control gate extensions formed within the recessed regions between the floating gates.

Abstract translation: 制造半导体存储器件的方法包括在半导体衬底的有源区上形成浮置栅极，并在浮置栅极上形成封盖层。 使用覆盖层作为蚀刻掩模对位于浮置栅极之间的半导体衬底中的隔离层进行各向异性蚀刻，以形成凹陷区域。 凹陷区域形成为具有小于浮动栅极之间的距离的宽度，以及位于浮动栅极的底表面下方的底表面的宽度。 控制栅电极形成在浮动栅极之上的有源区域两侧，并且控制栅电极具有形成在浮置栅极之间的凹陷区域内的控制栅延伸。

公开(公告)号：US07381508B2

公开(公告)日：2008-06-03

申请号：US10867468

申请日：2004-06-14

Applicant: Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

Inventor： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

IPC: G03F9/00 ,  G03F7/20

CPC classification number: H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

Abstract translation: 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

公开(公告)号：US07291531B2

公开(公告)日：2007-11-06

申请号：US11048995

申请日：2005-02-02

Applicant: Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

Inventor： Sung-Il Cho ,  Seung-Young Son ,  Chang-Jin Kang ,  Kyeong-Koo Chi ,  Ji-Chul Shin

IPC: H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/3142 ,  H01L21/31616 ,  H01L21/31645 ,  H01L21/32136 ,  H01L27/10855

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract translation: 提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。 例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中， 接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层 电极在下电极上。