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    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    33.
    发明申请
    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
    自对准嵌入式SiGe结构及其制造方法

    公开(公告)号：US20110298008A1

    公开(公告)日：2011-12-08

    申请号：US12795683

    申请日：2010-06-08

    申请人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    发明人： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

    摘要： A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

    摘要翻译： 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

    Structure and method to fabricate MOSFET with short gate
    34.
    发明授权
    Structure and method to fabricate MOSFET with short gate 有权
    用短栅制造MOSFET的结构和方法

    公开(公告)号：US07943467B2

    公开(公告)日：2011-05-17

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE
    35.
    发明申请
    SELF-ALIGNED WELL IMPLANT FOR IMPROVING SHORT CHANNEL EFFECTS CONTROL, PARASITIC CAPACITANCE, AND JUNCTION LEAKAGE 有权
    用于改善短路通道效应控制，对准电容和接头泄漏的自对准井

    公开(公告)号：US20110073961A1

    公开(公告)日：2011-03-31

    申请号：US12568287

    申请日：2009-09-28

    申请人： Robert H. Dennard ,  Brian J. Greene ,  Zhibin Ren ,  Xinlin Wang

    发明人： Robert H. Dennard ,  Brian J. Greene ,  Zhibin Ren ,  Xinlin Wang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/78654 ,  H01L29/78696

    摘要： A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a doped semiconductor layer beneath the undoped semiconductor layer; removing portions of the undoped semiconductor layer and the doped semiconductor layer left unprotected by the patterned gate structure, wherein a remaining portion of the undoped semiconductor layer beneath the patterned gate structure defines a transistor channel and a remaining portion of the doped semiconductor layer beneath the patterned gate structure defines the self-aligned well implant; and growing a new semiconductor layer at locations corresponding to the removed portions of the undoped semiconductor layer and the doped semiconductor layer, the new semiconductor layer corresponding to source and drain regions of the transistor.

    摘要翻译： 形成用于晶体管的自对准阱注入的方法包括在衬底上形成图案化栅极结构，该衬底包括栅极导体，栅极电介质层和侧壁间隔物，所述衬底包括在栅极介电层下面的未掺杂的半导体层，以及 未掺杂的半导体层下面的掺杂半导体层; 去除未图示的栅极结构保护的未掺杂半导体层和掺杂半导体层的部分，其中在图案化栅极结构下面的未掺杂半导体层的剩余部分限定晶体管沟道，并且掺杂半导体层的图案化下面的掺杂半导体层的剩余部分 栅极结构定义了自对准阱植入物; 以及在对应于未掺杂半导体层和掺杂半导体层的去除部分的位置处生长新的半导体层，新的半导体层对应于晶体管的源极和漏极区域。

    Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost
    36.
    发明授权
    Structure and method to form semiconductor-on-pores (SOP) for high device performance and low manufacturing cost 有权
    用于形成半导体上孔（SOP）的结构和方法，用于高器件性能和低制造成本

    公开(公告)号：US07842940B2

    公开(公告)日：2010-11-30

    申请号：US12062164

    申请日：2008-04-03

    申请人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

    发明人： Joel P. de Souza ,  Keith E. Fogel ,  Brian J. Greene ,  Devendra K. Sadana ,  Haining S. Yang

    IPC分类号： H01L31/00

    CPC分类号： H01L29/32 ,  H01L21/0203 ,  H01L21/76259 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/78

    摘要： A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

    摘要翻译： 提供了具有现有技术的SOI衬底的所有优点的半导体材料，包括例如低寄生电容和泄漏，而不具有浮体效应。 更具体地说，本发明提供一种包括顶部半导体层和底部半导体层的半导体激光器（SOP）材料，其中半导体层通过多孔半导体材料在至少一个区域中分离。 还提供了包括作为基板的SOP材料的半导体结构以及制造SOP材料的方法。 该方法包括：形成具有第一半导体层的p型区域，将p型区域转换为多孔半导体材料，通过退火密封多孔半导体材料的上表面，以及在多孔半导体材料的顶部形成第二半导体层 。

    Method and structure for reducing induced mechanical stresses
    38.
    发明授权
    Method and structure for reducing induced mechanical stresses 有权
    减少诱导机械应力的方法和结构

    公开(公告)号：US07572689B2

    公开(公告)日：2009-08-11

    申请号：US11937637

    申请日：2007-11-09

    申请人： Brian J. Greene ,  Rajesh Rengarajan

    发明人： Brian J. Greene ,  Rajesh Rengarajan

    IPC分类号： H01L21/337

    CPC分类号： H01L21/823425 ,  H01L21/823412 ,  H01L29/6653 ,  H01L29/7843

    摘要： Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.

    摘要翻译： 在应力半导体衬垫中减轻应力的方法和结构。 增强NFET或PFET性能的应力衬垫沉积在半导体上以覆盖NFET和PFET。 沉积一次性层以完全覆盖应力衬垫NFET和PFET。 这种一次性层被选择性地凹入以仅暴露出不受这种应力衬垫增强的NFET或PFET的栅极上的单个应力衬垫，然后去除该暴露的衬垫以露出这种栅极的顶部。 去除一次性层的剩余部分，从而增强NFET或PFET的性能，同时避免NFET或PFET不受应力衬垫增强的劣化。 单应力衬垫是用于增强NFET性能的拉伸应力衬垫，或者是用于增强PFET性能的压应力衬垫。