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    TRANSISTOR AND METHOD OF FABRICATING THE SAME
    32.
    发明申请
    TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
    晶体管及其制造方法

    公开(公告)号：US20150318363A1

    公开(公告)日：2015-11-05

    申请号：US14800251

    申请日：2015-07-15

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Sung Haeng CHO ,  Sang-Hee PARK ,  Chi-Sun HWANG

    IPC: H01L29/417 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

    Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

    GATE DRIVER CIRCUIT OUTPUTTING SUPERIMPOSED PULSES
    34.
    发明申请
    GATE DRIVER CIRCUIT OUTPUTTING SUPERIMPOSED PULSES 审中-公开
    门驱动电路输出超级脉冲

    公开(公告)号：US20150171833A1

    公开(公告)日：2015-06-18

    申请号：US14335242

    申请日：2014-07-18

    Applicant: Konkuk University Industrial Cooperation Corp ,  Electronics and Telecommunications Research Institute

    Inventor： Jae-Eun PI ,  Sang-Hee PARK ,  Min Ki RYU ,  Chi-Sun HWANG ,  OhSang KWON ,  Eunsuk PARK ,  Kee-Chan PARK ,  YeonKyung KIM

    IPC: H03K3/012 ,  H03K5/01

    CPC classification number: H03K3/012 ,  H03K4/026 ,  H03K5/01 ,  H03K5/05

    Abstract: Provided is a gate driver circuit. The gate driver circuit includes a plurality of sequentially connected stages, and each of stages includes an input unit including two input transistors forming diode connection, a pull-up unit including a pull-up transistor and a bootstrap capacitor, and first and second pull-down units each including two transistors. According to embodiments, an input capacitor is further included which is connected to a node between the input unit and the pull-up unit. In addition, a carry unit is further included which is connected to an output terminal and formed to transmit an output signal in a high state or a low state to a next stage.

    Abstract translation: 提供了一个栅极驱动电路。 栅极驱动器电路包括多个顺序连接的级，并且每个级包括一个输入单元，该输入单元包括形成二极管连接的两个输入晶体管，一个包括上拉晶体管和自举电容器的上拉单元，以及第一和第二上拉电路， 每个下降单元包括两个晶体管。 根据实施例，还包括输入电容器，其连接到输入单元和上拉单元之间的节点。 此外，还包括进位单元，其连接到输出端子并且被形成为将处于高状态或低状态的输出信号传输到下一级。

    OXIDE TRANSISTOR WITH NANO-LAYERED STRUCTURE AND METHOD OF FABRICATING THE SAME
    35.
    发明申请
    OXIDE TRANSISTOR WITH NANO-LAYERED STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
    具有纳米结构的氧化物晶体及其制造方法

    公开(公告)号：US20140159036A1

    公开(公告)日：2014-06-12

    申请号：US14020498

    申请日：2013-09-06

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Su Jae LEE ,  Chi-Sun HWANG ,  Hye Yong CHU ,  Sang Chul LIM ,  Jae-Eun PI ,  Min Ki RYU

    IPC: H01L29/786 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L29/66969 ,  H01L29/78696

    Abstract: According to example embodiments of the inventive concept, provided is a transistor with a nano-layered oxide semiconductor layer. The oxide semiconductor layer may include at least one first nano layer and at least one second nano layer that are alternatingly stacked one on another. Here, the first nano layer and the second nano layer may include different materials from each other, and thus, a channel with high electron mobility may be formed at the interface between the first and second nano layers. Accordingly, the transistor can have high reliability.

    Abstract translation: 根据本发明构思的示例性实施例，提供了具有纳米层氧化物半导体层的晶体管。 氧化物半导体层可以包括交替堆叠在一起的至少一个第一纳米层和至少一个第二纳米层。 这里，第一纳米层和第二纳米层可以包括彼此不同的材料，因此，可以在第一和第二纳米层之间的界面处形成具有高电子迁移率的沟道。 因此，晶体管可以具有高的可靠性。

    SPATIAL LIGHT MODULATOR
    39.
    发明申请
    SPATIAL LIGHT MODULATOR 有权

    公开(公告)号：US20210034013A1

    公开(公告)日：2021-02-04

    申请号：US16846857

    申请日：2020-04-13

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Seong-Mok CHO ,  Yong Hae KIM ,  Sang Hoon CHEON ,  Kyunghee CHOI ,  Chi-Sun HWANG

    IPC: G03H1/22 ,  G02F1/01

    Abstract: A spatial light modulator according to the inventive concept includes a light modulation layer including a plurality of pixels arranged on a plane perpendicular to a first direction, a first lens array including first lenses corresponding one-to-one with the pixels, a second lens array including second lenses corresponding one-to-one with the first lenses, and a spacer layer between the first lens array and the second lens array. Each of the first lenses has a first central axis extending in the first direction and the first central axes of the first lenses meet at different positions for each of the pixels.

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