公开(公告)号：US06181014B2

公开(公告)日：2001-01-30

申请号：US09271519

申请日：1999-03-18

申请人： Kyu-Charn Park ,  Duck-Hyung Lee

发明人： Kyu-Charn Park ,  Duck-Hyung Lee

IPC分类号： H01L2348

CPC分类号： H01L27/10858 ,  H01L27/10885 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： Integrated circuit memory devices having highly integrated SOI memory cells therein include an SOI substrate having a semiconductor active layer therein. A first trench isolation region is also provided. The first trench isolation region extends into and partitions the semiconductor active layer into first and second active regions. These first and second active regions are preferably electrically isolated from each other by the first trench isolation region. First and second access transistors are provided in the first and second active regions, respectively, and a first electrically insulating layer is provided on the SOI substrate. A first bit line is also provided at a first level. The first bit line is electrically connected to a first source/drain region of the first access transistor by a first bit line contact. This first bit line contact extends through the first electrically insulating layer and contacts the first source/drain region of the first access transistor. A second electrically insulating layer is also provided on the first bit line, opposite said first electrically insulating layer and a second bit line is provided on the second electrically insulating layer at a second level above the first level. The second bit line is electrically connected to a first source/drain region of the second access transistor by a second bit line contact which extends through the first and second electrically insulating layers and contacts the first source/drain region of the second access transistor. Higher integration densities can be achieved by dividing the active layer into electrically isolated active regions and then forming bit lines at different levels which are electrically connected to access transistors within these isolated active regions.

摘要翻译： 其中具有高度集成的SOI存储单元的集成电路存储器件包括其中具有半导体有源层的SOI衬底。 还提供了第一沟槽隔离区域。 第一沟槽隔离区延伸到半导体活性层并将其分隔成第一和第二有源区。 这些第一和第二有源区优选地通过第一沟槽隔离区彼此电隔离。 第一和第二存取晶体管分别设置在第一和第二有源区中，并且第一电绝缘层设置在SOI衬底上。 在第一级还提供第一位线。 第一位线通过第一位线接触电连接到第一存取晶体管的第一源极/漏极区域。 该第一位线接触件延伸穿过第一电绝缘层并接触第一存取晶体管的第一源极/漏极区域。 在第一位线上还设有第二电绝缘层，与第一电绝缘层相对，并且第二位线在第二电绝缘层上设置在高于第一电平的第二电平上。 第二位线通过延伸穿过第一和第二电绝缘层并接触第二存取晶体管的第一源/漏区的第二位线接触电连接到第二存取晶体管的第一源/漏区。 可以通过将有源层分为电隔离的有源区，然后形成与这些隔离的有源区内的存取晶体管电连接的不同电平的位线来实现更高的积分密度。

公开(公告)号：US08809932B2

公开(公告)日：2014-08-19

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US08076713B2

公开(公告)日：2011-12-13

申请号：US12422862

申请日：2009-04-13

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US20110076812A1

公开(公告)日：2011-03-31

申请号：US12959814

申请日：2010-12-03

申请人： Choong-Ho LEE ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Choong-Ho LEE ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L21/336

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L24/32 ,  H01L24/83 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7781 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/792 ,  H01L2224/2919 ,  H01L2224/838 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0665 ,  H01L2924/00

摘要： A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

摘要翻译： 半导体器件包括第一衬底，多个单元晶体管和第二衬底。 第一基板具有与第一表面相对的第一表面和第二表面。 多个单元晶体管形成在第一基板的第一表面上沿一个方向延伸。 第二基板具有与第一基板的第二表面接触的上表面。 此外，第二基板的上表面具有弯曲结构，以在多个单元晶体管的延伸方向上向第一基板施加拉伸应力。 因此，可以向第一衬底施加拉伸应力以改善电池晶体管的沟道区域中载流子的迁移率。

公开(公告)号：US07915138B2

公开(公告)日：2011-03-29

申请号：US12485577

申请日：2009-06-16

申请人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

发明人： Hye-Jin Cho ,  Kyu-Charn Park ,  Choong-Ho Lee ,  Byung-Yong Choi

IPC分类号： H01L21/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

摘要翻译： 在制造非易失性存储器件的方法中，在衬底上形成导电结构。 导电结构包括隧道氧化物图案，第一导电图案，衬垫氧化物图案和硬掩模图案。 使用导电结构作为蚀刻掩模在衬底上形成沟槽。 在沟槽的内壁和隧道氧化物图案的侧壁和第一导电图案上形成内部氧化物层。 内部氧化物层被固化，从而在内部氧化物层上形成氮化硅层。 在沟槽中形成器件隔离图案，并且从衬底去除硬掩模图案和衬垫氧化物图案。 在基板上形成电介质层和第二导电图案。 因此，氮化硅层防止氢（H）原子泄漏到器件隔离图案中。

公开(公告)号：US07883929B2

公开(公告)日：2011-02-08

申请号：US12035169

申请日：2008-02-21

申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

IPC分类号： H01L31/00

CPC分类号： H01L45/165 ,  H01L27/2436 ,  H01L45/085 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/146

摘要： Integrated circuit nonvolatile memory devices are manufactured by forming a variable resistance layer on an integrated circuit substrate. The variable resistance layer includes grains that define grain boundaries between the grains. Conductive filaments are formed along at least some of the grain boundaries. Electrodes are formed on the variable resistance layer. The conductive filaments may be formed by implanting conductive ions into at least some of the grain boundaries. Moreover, the variable resistance layer may be a variable resistance oxide of a metal, and the conductive filaments may be the metal. Related devices are also disclosed.

摘要翻译： 通过在集成电路基板上形成可变电阻层来制造集成电路非易失性存储器件。 可变电阻层包括限定晶粒之间的晶界的晶粒。 沿着至少一些晶界形成导电丝。 电极形成在可变电阻层上。 可以通过将导电离子注入至少一些晶界来形成导电细丝。 此外，可变电阻层可以是金属的可变电阻氧化物，并且导电丝可以是金属。 还公开了相关设备。

公开(公告)号：US07868467B2

公开(公告)日：2011-01-11

申请号：US12167875

申请日：2008-07-03

申请人： Choong-Ho Lee ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Choong-Ho Lee ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L29/40

CPC分类号： H01L29/045 ,  H01L21/823412 ,  H01L24/32 ,  H01L24/83 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/7781 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/792 ,  H01L2224/2919 ,  H01L2224/838 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0665 ,  H01L2924/00

摘要： A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.

摘要翻译： 半导体器件包括第一衬底，多个单元晶体管和第二衬底。 第一基板具有与第一表面相对的第一表面和第二表面。 多个单元晶体管形成在第一基板的第一表面上沿一个方向延伸。 第二基板具有与第一基板的第二表面接触的上表面。 此外，第二基板的上表面具有弯曲结构，以在多个单元晶体管的延伸方向上向第一基板施加拉伸应力。 因此，可以向第一衬底施加拉伸应力以改善电池晶体管的沟道区域中载流子的迁移率。

公开(公告)号：US20090250747A1

公开(公告)日：2009-10-08

申请号：US12422862

申请日：2009-04-13

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US07508048B2

公开(公告)日：2009-03-24

申请号：US10758802

申请日：2004-01-15

申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

IPC分类号： H01L29/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。

公开(公告)号：US20080123399A1

公开(公告)日：2008-05-29

申请号：US11943657

申请日：2007-11-21

申请人： Byung Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

发明人： Byung Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/105 ,  H01L27/101 ,  H01L27/112

摘要： A non-volatile memory device includes a substrate having a recess thereon, a resistant material layer pattern in the recess, a lower electrode on the resistant material layer pattern in the recess, a dielectric layer, and an upper electrode formed on the dielectric layer. The resistant material layer pattern includes a material whose resistance varies according to an applied voltage. The dielectric layer is formed on the substrate, the resistant material layer pattern and the lower electrode. An upper electrode overlaps the resistant material layer pattern and the lower electrode. The applied voltage is applied to access the upper and lower electrodes to vary the resistance of the resistant material layer pattern.

摘要翻译： 非易失性存储器件包括其上具有凹部的衬底，凹部中的电阻材料层图案，凹部中的电阻材料层图案上的下电极，形成在电介质层上的电介质层和上电极。 电阻材料层图案包括其电阻根据施加的电压而变化的材料。 介电层形成在基板上，电阻材料层图案和下电极上。 上电极与电阻材料层图案和下电极重叠。 施加施加的电压以访问上电极和下电极以改变电阻材料层图案的电阻。