公开(公告)号：US06780713B2

公开(公告)日：2004-08-24

申请号：US10167959

申请日：2002-06-11

申请人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

发明人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

IPC分类号： H01L21336

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

摘要翻译： 在制造DMOS晶体管的新工艺中，倾斜侧壁的掺杂可以独立于沟槽结构中底层区域的掺杂来设置。 此外，可以在侧壁之间建立不同的掺杂。 这通过一系列注入掺杂，蚀刻形成沟槽，在侧壁上形成散射氧化物保护层以及两级垂直和倾斜的最终注入掺杂来实现。 对于DMOS晶体管，即使使用低导通电阻也能实现高的突破电压，并且特别是关于驱动器结构，减少了空间需求。

公开(公告)号：US07923362B2

公开(公告)日：2011-04-12

申请号：US11447094

申请日：2006-06-06

申请人： Franz Dietz ,  Volker Dudek ,  Tobias Florian ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Tobias Florian ,  Michael Graf

IPC分类号： H01L21/28

CPC分类号： H01L21/28537 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L27/095 ,  H01L29/66143 ,  H01L31/108 ,  H01L31/18

摘要： A method for manufacturing a metal-semiconductor contact in semiconductor Components is disclosed. There is a relatively high risk of contamination in the course of metal depositions in prior-art methods. In the disclosed method, the actual metal -semiconductor or Schottky contact is produced only after the application of a protective layer system, as a result of which it is possible to use any metals, particularly platinum, without the risk of contamination.

摘要翻译： 公开了一种半导体元件中的金属 - 半导体接触的制造方法。 在现有技术方法中金属沉积过程中存在较高的污染风险。 在所公开的方法中，仅在施加保护层系统之后才产生实际的金属 - 半导体或肖特基接触，其结果是可以使用任何金属，特别是铂，而不会有污染的风险。

公开(公告)号：US20070264792A1

公开(公告)日：2007-11-15

申请号：US11812386

申请日：2007-06-18

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Thomas Hoffmann

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method for producing deep trench structures in an STI structure of a semiconductor substrate is provided, with the following successive process steps: subsequent to a full-area filling of STI recesses introduced into a semiconductor substrate with a first filler material, a first surface of a semiconductor structure is subjected to a CMP process to level the applied filler material and produce the STI structure; the leveled STI structure thus produced is structured; using the structured, leveled STI structure as a hard mask, at least one deep trench is etched in the area of this STI structure to create the deep trench structures.

摘要翻译： 提供了一种用于在半导体衬底的STI结构中制造深沟槽结构的方法，其具有以下连续的工艺步骤：在用第一填充材料引入到半导体衬底中的STI凹部的全面填充之后， 对半导体结构进行CMP处理以对施加的填充材料进行平整并产生STI结构; 这样生产的水平STI结构是结构化的; 使用结构化的水平STI结构作为硬掩模，在该STI结构的区域中蚀刻至少一个深沟槽以产生深沟槽结构。

公开(公告)号：US20070132019A1

公开(公告)日：2007-06-14

申请号：US11636668

申请日：2006-12-11

申请人： Franz Dietz ,  Michael Graf ,  Stefan Schwantes

发明人： Franz Dietz ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/76

CPC分类号： H01L29/0696 ,  H01L29/0886 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral DMOS transistor is disclosed that includes a first region of a first conductivity type, which is surrounded on the sides by a second region of a second conductivity type, whereby a boundary line between both regions has opposite straight sections and curved sections linking the straight sections, and with a first dielectric structure, which serves as a field region and is embedded in the first region and surrounds a subregion of the first region. Whereby the first distance between the first dielectric structure and the boundary line is greater along the straight sections than along the curved sections.

摘要翻译： 公开了一种横向DMOS晶体管，其包括第一导电类型的第一区域，其在侧面被第二导电类型的第二区域包围，由此两个区域之间的边界线具有相对的直线部分和连接直线的弯曲部分 并且具有用作场区域并被嵌入在第一区域中并且围绕第一区域的子区域的第一电介质结构。 由此，第一电介质结构和边界线之间的第一距离沿着直线部分比沿着弯曲部分更大。

公开(公告)号：US07189619B2

公开(公告)日：2007-03-13

申请号：US11045382

申请日：2005-01-31

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L21/76

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L29/7812 ,  H01L29/7824

摘要： Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

摘要翻译： 制造具有绝缘层的SOI晶片中具有不同厚度的垂直绝缘的有源半导体区域。 在晶片上，具有第一厚度的第一有源半导体区域被布置在有源半导体材料层中。 具有相对较小厚度的第二有源半导体区域通过从沟槽结构中的至少一个种子开口进行的外延生长产生。 第二半导体区域通过氧化物层从第一半导体区域基本上完全介电绝缘，横向和垂直地绝缘。 种子开口的宽度可以通过光刻来定义。

公开(公告)号：US07144796B2

公开(公告)日：2006-12-05

申请号：US10946506

申请日：2004-09-20

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/22 ,  H01L21/8238

CPC分类号： H01L29/66659 ,  H01L21/2253 ,  H01L21/26586 ,  H01L21/76237 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1045 ,  H01L29/7835

摘要： A semiconductor element such as a DMOS-transistor is fabricated in a semiconductor substrate. Wells of opposite conductivity are formed by implanting and then thermally diffusing respective well dopants into preferably spaced-apart areas in the substrate. At least one trench and active regions are formed in the substrate. The trench may be a shallow drift zone trench of a DMOS-transistor, and/or a deep isolation trench. The thermal diffusion of the well dopants includes at least one first diffusion step during a first high temperature drive before forming the trench, and at least one second diffusion step during a second high temperature drive after forming the trench. Dividing the thermal diffusion steps before and after the trench formation achieves an advantageous balance between reducing or avoiding lateral overlapping diffusion of neighboring wells and reducing or avoiding thermally induced defects along the trench boundaries.

摘要翻译： 在半导体衬底中制造诸如DMOS晶体管的半导体元件。 相反电导率的阱通过注入然后将各个掺杂剂热扩散到衬底中优选间隔开的区域中而形成。 在衬底中形成至少一个沟槽和有源区。 沟槽可以是DMOS晶体管的浅漂移区沟槽和/或深隔离沟槽。 阱掺杂剂的热扩散包括在形成沟槽之前的第一高温驱动期间的至少一个第一扩散步骤，以及在形成沟槽之后的第二高温驱动期间的至少一个第二扩散步骤。 在沟槽形成之前和之后划分热扩散步骤在减少或避免相邻阱的横向重叠扩散之间实现有利的平衡，并减少或避免沿着沟槽边界的热诱导缺陷。

公开(公告)号：US20050170571A1

公开(公告)日：2005-08-04

申请号：US11048963

申请日：2005-01-31

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L21/00 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/76264 ,  H01L21/84

摘要： An SOI wafer including an active semiconductor material layer on an insulating layer is processed to form thereon first and second active semiconductor regions that respectively have different thicknesses and that are vertically and laterally insulated. In the process, a trench is etched into the SOI wafer, seed openings are formed in the bottom of the trench to reach the underlying active material layer, the trench is filled with epitaxially grown semiconductor material progressing from the seed openings, some of the epitaxially grown material is removed to form the second active regions, and oxide layers are provided so that the second active regions are laterally and vertically insulated from the first active regions formed by remaining portions of the active semiconductor material layer.

摘要翻译： 处理包括绝缘层上的有源半导体材料层的SOI晶片，以在其上形成分别具有不同厚度并且垂直和横向绝缘的第一和第二有源半导体区域。 在该过程中，沟槽被蚀刻到SOI晶片中，种子开口形成在沟槽的底部以到达下面的活性材料层，沟槽填充有从种子开口进行的外延生长的半导体材料，一些外延 去除生长材料以形成第二有源区，并且提供氧化物层，使得第二有源区域与由有源半导体材料层的剩余部分形成的第一有源区域横向和垂直地绝缘。

公开(公告)号：US20090258472A1

公开(公告)日：2009-10-15

申请号：US11528400

申请日：2006-09-28

申请人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

发明人： Tobias Florian ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L21/762

CPC分类号： H01L29/7824 ,  H01L21/743 ,  H01L21/76205 ,  H01L21/76251 ,  H01L21/76286 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/66681 ,  H01L29/78603 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

摘要： Method for manufacturing a semiconductor array, in which a conductive substrate (100), a component region (400), and an insulation layer (200), isolating the component region (400) from the conductive substrate (100), are formed, a trench (700) is etched in the component region (400) as far as the insulation layer (200), then the trench (700) is etched further as far as the conductive substrate (100), the walls (701) of the trench (700) are formed with an insulation material (710), and an electrical conductor (750, 755, 760) is introduced into the trench (700) and connected conductively to the conductive substrate (100), wherein before the trench (700) is etched, a layer sequence comprising a first oxide layer (510), a polysilicon layer (520) on top of the first oxide layer (510), and a second oxide layer (530) on top of the polysilicon layer (520) is applied to the component region (400).

摘要翻译： 形成半导体阵列的方法，其中，形成将导电基板（100）与元件区域（400）隔离的导电基板（100），部件区域（400）和绝缘层（200） 沟槽（700）在分隔区域（400）中被蚀刻到绝缘层（200），然后将沟槽（700）进一步蚀刻到导电基底（100），沟槽（701）的壁 （700）形成有绝缘材料（710），并且电导体（750,755,760）被引入到沟槽（700）中并且导电地连接到导电衬底（100），其中在沟槽（700）之前， 被蚀刻，包括在第一氧化物层（510）的顶部上的第一氧化物层（510），多晶硅层（520）和在多晶硅层（520）的顶部上的第二氧化物层（530）的层序列是 施加到部件区域（400）。

公开(公告)号：US20110260250A1

公开(公告)日：2011-10-27

申请号：US13174398

申请日：2011-06-30

申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

摘要： By aligning the primary flat of a wafer with a (100) plane rather than a (110) plane, devices can be formed with primary currents flowing along the (100) plane. In this case, the device will intersect the (111) plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the (111) direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.

摘要翻译： 通过将晶片的主平面与（100）平面而不是（110）平面对准，可以沿着（100）平面流动的初级电流形成器件。 在这种情况下，设备将以大约54.7度与（111）平面相交。 这个相交角度可以显着地减少沿（111）方向的应力传播/释放，从而减少缺陷以及泄漏和寄生电流。 泄漏电流降低是短路源极 - 漏极结所需的位错长度变化的直接后果。 通过使用这种技术，对于N沟道CMOS器件，泄漏电流降低高达两个数量级。

公开(公告)号：US20050064678A1

公开(公告)日：2005-03-24

申请号：US10945720

申请日：2004-09-20

申请人： Volker Dudek ,  Michael Graf

发明人： Volker Dudek ,  Michael Graf

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232

摘要： To form a semiconductor component having active regions separated from one another by trenches as isolation structures, a method involves forming a shallow trench in a semiconductor body, thereafter forming a deep trench within the shallow trench in the semiconductor body, and thereafter completely driving dopant atoms into the semiconductor body to form a well region doped with the dopant. The dopant may be previously introduced by implantation into a surface layer, and then the dopant is finally completely driven into the well region by thermally supported diffusion after forming the deep trench. The shallow and deep trenches together form a compound trench with stepped side walls. Two oppositely doped wells may be formed on opposite sides of the compound trench, which thus isolates the two wells from one another. Active regions may be formed in the two wells.

摘要翻译： 为了形成具有通过沟槽作为隔离结构彼此分离的有源区的半导体部件，包括在半导体本体中形成浅沟槽，之后在半导体本体内的浅沟槽内形成深沟槽，然后完全驱动掺杂原子 进入半导体体以形成掺杂有掺杂剂的阱区。 可以预先通过注入掺杂剂到表面层中，然后在形成深沟槽之后通过热支持的扩散将掺杂剂最终完全驱动到阱区中。 浅沟槽和深沟槽一起形成具有阶梯状侧壁的复合沟槽。 可以在复合沟槽的相对侧上形成两个相对掺杂的阱，从而将两个阱彼此隔离。 活性区域可以形成在两个孔中。