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    System and method for monitoring strain
    31.
    发明授权
    System and method for monitoring strain 有权
    用于监测应变的系统和方法

    公开(公告)号：US09279666B1

    公开(公告)日：2016-03-08

    申请号：US14558170

    申请日：2014-12-02

    Applicant: GENERAL ELECTRIC COMPANY

    Inventor： Mahadevan Balasubramaniam ,  Slawomir Rubinsztajn ,  Glen Peter Koste ,  Kaustubh Ravindra Nagarkar ,  Vincent Frank Rubino ,  Jeffrey Roy Rudd ,  Paul Jeffrey Gillespie

    IPC: G01L1/24 ,  G01B11/16

    CPC classification number: G01B11/165 ,  G01B11/18 ,  G01L1/246

    Abstract: A system is provided for monitoring strain in a substrate using a strain sensor element within a fiber optic sensing cable. Accurate and rapid measurement of strain of remote substrates presents major technical challenges and is the focus of much of the description presented. However, systems, methods and devices provided by the present invention are not only capable of reliably measuring strain in real time, but are also capable of measuring other characteristics of a substrate such as its temperature, pressure and its acoustic characteristics. The system is configured such that a strain sensor element within a strain sensing zone detects substantially the true strain characteristics of the substrate. And while other sensing elements within the same fiber optic sensing cable may not be configured to detect substrate strain at all, these sensing elements may reliably measure the temperature and pressure at the surface of the substrate adjacent to the strain sensing zone.

    Abstract translation: 提供一种系统，用于使用光纤传感电缆内的应变传感器元件来监测衬底中的应变。 对远程基板的应变的准确和快速测量提出了主要的技术挑战，并且是所提出的大部分描述的重点。 然而，本发明提供的系统，方法和装置不仅可以实时可靠地测量应变，而且能够测量诸如其温度，压力和其声学特性的基板的其它特性。 该系统被配置为使得应变传感区域内的应变传感器元件基本上检测到基板的真实应变特性。 而同一光纤传感电缆内的其它传感元件根本不能配置为检测基板应变，这些传感元件可以可靠地测量与应变感测区相邻的基板表面处的温度和压力。

    Electronics package for light emitting semiconductor devices and method of manufacturing thereof
    33.
    发明授权
    Electronics package for light emitting semiconductor devices and method of manufacturing thereof 有权

    公开(公告)号：US10957832B2

    公开(公告)日：2021-03-23

    申请号：US16166313

    申请日：2018-10-22

    Applicant: General Electric Company

    Inventor： Christopher James Kapusta ,  Risto Ilkka Sakari Tuominen ,  Kaustubh Ravindra Nagarkar

    IPC: H01L33/62 ,  H01L23/538 ,  H01L33/54 ,  H01L33/60 ,  H01L25/075 ,  H01L25/16 ,  H01L33/64

    Abstract: A light emitting semiconductor (LES) device having desirable thermal performance characteristics is disclosed. The LES device includes an insulating substrate layer having a plurality of vias formed therein and at least one LES chip mounted on the insulating substrate layer, with each of the LES chips(s) including an active surface including a light emitting area configured to emit light therefrom and a back surface positioned on a top surface of the insulating substrate layer and including connection pads thereon. A conductor layer is positioned on a bottom surface of the insulating substrate layer and in the vias, the conductor layer in direct contact with the connection pads of the LES chip(s) so as to be electrically and thermally connected thereto. An encapsulant is positioned adjacent the top surface of the insulating substrate layer and surrounding at least part of the LES chip(s), the encapsulant comprising a light transmitting material.

    Semiconductor logic device and system and method of embedded packaging of same
    36.
    发明授权
    Semiconductor logic device and system and method of embedded packaging of same 有权

    公开(公告)号：US10396053B2

    公开(公告)日：2019-08-27

    申请号：US15816396

    申请日：2017-11-17

    Applicant: General Electric Company

    Inventor： Raymond Albert Fillion ,  Kaustubh Ravindra Nagarkar

    IPC: H01L23/00 ,  H01L23/50

    Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising an active surface having a plurality of input/output (I/O) pads formed thereon and a redistribution layer. The redistribution layer includes an insulating layer disposed on the active surface of the semiconductor logic device and a patterned conductive layer comprising a plurality of discrete terminal pads formed atop the insulating layer. The plurality of discrete terminal pads are electrically coupled to respective I/O pads of the plurality of I/O pads by conductive vias formed through the insulating layer. The plurality of discrete terminal pads are larger than the plurality of I/O pads.

    Embedded RF filter package structure and method of manufacturing thereof
    38.
    发明授权
    Embedded RF filter package structure and method of manufacturing thereof 有权

    公开(公告)号：US10333493B2

    公开(公告)日：2019-06-25

    申请号：US15246671

    申请日：2016-08-25

    Applicant: General Electric Company

    Inventor： Kaustubh Ravindra Nagarkar ,  Yongjae Lee ,  Christopher James Kapusta

    IPC: H03H9/64 ,  H03H9/72 ,  H03H9/54 ,  H03H3/02 ,  H03H9/05 ,  H03H9/10

    Abstract: A filter package and method of manufacturing thereof is disclosed. The filter device package includes a first dielectric layer having an acoustic wave filter device attached thereto, the acoustic wave filter device comprising an active area and I/O pads. The filter device package also includes an adhesive positioned between the first dielectric layer and the acoustic wave filter device to secure the layer to the device, vias formed through the first dielectric layer and the adhesive to the I/O pads of the acoustic wave filter device, and metal interconnects formed in the vias and mechanically and electrically coupled to the I/O pads of the acoustic wave filter device to form electrical interconnections thereto, wherein an air cavity is formed in the adhesive between the acoustic wave filter device and the first dielectric layer, in a location adjacent the active area of the acoustic wave filter device.

    ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME
    40.
    发明申请
    ELECTRONICS PACKAGE HAVING A SELF-ALIGNING INTERCONNECT ASSEMBLY AND METHOD OF MAKING SAME 审中-公开

    公开(公告)号：US20190148279A1

    公开(公告)日：2019-05-16

    申请号：US16229049

    申请日：2018-12-21

    Applicant: General Electric Company

    Inventor： Christopher James Kapusta ,  Kaustubh Ravindra Nagarkar ,  Arun Virupaksha Gowda ,  James Wilson Rose

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: An electronics package includes an interconnect assembly comprising a first insulating substrate, a first wiring layer formed on a lower surface of the first insulating substrate, and at least one through hole extending through the first insulating substrate and the first wiring layer. The electronics package also includes an electrical component assembly comprising an electrical component having an active surface coupled to an upper surface of the first insulating substrate opposite the lower surface. The active surface of the electrical comprises at least one metallic contact pad. At least one conductive stud is coupled to the at least one metallic contact pad and is positioned within the at least one through hole. A conductive plug contacts the first wiring layer and extends into the at least one through hole to at least partially surround the at least one conductive stud.

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