公开(公告)号：US20150084183A1

公开(公告)日：2015-03-26

申请号：US14033789

申请日：2013-09-23

Applicant: Globalfoundries, Inc.

Inventor： Joachim Patzer ,  Hans-Peter Moll

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/28512 ,  H01L21/76886 ,  H01L27/0629 ,  H01L28/20

Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract translation: 为具有晶体管和电阻器的集成电路提供了方法和装置。 该方法包括在晶体管和电阻器之上沉积第一介电层，随后是非晶硅层。 将非晶硅层注入电阻器上以产生蚀刻掩模，并且在晶体管上去除非晶硅层和第一介电层。 然后将晶体管上的接触位置硅化。

公开(公告)号：US10224251B2

公开(公告)日：2019-03-05

申请号：US15667017

申请日：2017-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Gunter Grasshoff

IPC: H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12

Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.

公开(公告)号：US20170162557A1

公开(公告)日：2017-06-08

申请号：US14958150

申请日：2015-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Juergen Faul

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12 ,  H01L27/07 ,  H01L49/02

CPC classification number: H01L27/0222 ,  G05F3/205 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/40 ,  H01L29/665 ,  H01L29/945

Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.

公开(公告)号：US20170067955A1

公开(公告)日：2017-03-09

申请号：US14848804

申请日：2015-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Uwe Dersch ,  Ricardo Pablo. Mikalo

IPC: G01R31/26 ,  G01R31/02 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/08

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/42384

Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.

Abstract translation: 提供半导体测试结构用于检测凸起的源极/漏极区域 - 包括半导体衬底的栅极电极短路，形成在半导体衬底上的FET，形成在半导体衬底上的FET的升高的源极/漏极区域，包括多个 所述FET的栅电极彼此平行地布置，以及电连接到所述栅电极结构的第一电端子，并且其中在所述栅极电极结构的所述多个栅电极之间没有与所述凸起的源极/漏极区的电接触。

公开(公告)号：US09553046B2

公开(公告)日：2017-01-24

申请号：US14718502

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Peter Baars ,  Hans-Peter Moll

IPC: H01L21/331 ,  H01L23/525 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5256 ,  H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor device comprising a fuse is provided including providing a semiconductor-on-insulator (SOI) structure comprising an insulating layer and a semiconductor layer formed on the insulating layer, forming raised semiconductor regions on the semiconductor layer adjacent to a central portion of the semiconductor layer and performing a silicidation process of the central portion of the semiconductor layer and the raised semiconductor regions to form a silicided semiconductor layer and silicided raised semiconductor regions.

Abstract translation: 提供一种形成包括熔丝的半导体器件的方法，包括：提供绝缘层上的绝缘体上半导体结构（SOI）结构和形成在绝缘层上的半导体层，在与中心相邻的半导体层上形成凸起的半导体区域 并且对半导体层的中心部分和凸起的半导体区域进行硅化处理，以形成硅化半导体层和硅化凸起的半导体区域。

公开(公告)号：US09502564B2

公开(公告)日：2016-11-22

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160315016A1

公开(公告)日：2016-10-27

申请号：US14695232

申请日：2015-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/76264 ,  H01L21/84 ,  H01L21/845 ,  H01L27/127 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78648 ,  H01L29/78684

Abstract: A method of forming a semiconductor device is provided including providing a semiconductor-on-insulator (SOI) wafer comprising a first semiconductor layer comprising a first material component and formed on a buried oxide (BOX) layer, and forming a channel region of a P-channel transistor device, including forming a second semiconductor layer only over a first portion of the first semiconductor layer, wherein the second semiconductor layer comprises the first material component and a second material component different from the first material component, forming an opening in the first semiconductor layer outside the first portion and subsequently performing a thermal anneal to push the second material component from the second semiconductor layer into the first semiconductor layer.

Abstract translation: 提供一种形成半导体器件的方法，包括：提供绝缘体上半导体（SOI）晶片，其包括第一半导体层，其包含第一材料成分并形成在掩埋氧化物（BOX）层上，并形成P 通道晶体管器件，包括只在第一半导体层的第一部分上形成第二半导体层，其中第二半导体层包括第一材料成分和与第一材料成分不同的第二材料成分，在第一 半导体层，然后进行热退火，以将第二材料成分从第二半导体层推入第一半导体层。

公开(公告)号：US20160268431A1

公开(公告)日：2016-09-15

申请号：US15164374

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: A semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and a buried insulating material region disposed in the active region under the gate structure. The buried insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth of the active region. The source/drain regions have a depth greater than a top surface of the buried insulating material region.

Abstract translation: 半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅结构对准的有源区中的源极/漏极区，以及设置在有源区内的掩埋绝缘材料区 门结构。 掩埋绝缘材料区域被有源区域包围，并且沿着有源区域的深度与栅极结构下方的有源区域中的沟道区域相邻。 源/漏区具有大于掩埋绝缘材料区的顶表面的深度。

公开(公告)号：US20160204128A1

公开(公告)日：2016-07-14

申请号：US14592069

申请日：2015-01-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/321 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L49/02 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: A method of forming a semiconductor device structure includes providing a substrate with a semiconductor-on-insulator (SOI) configuration, the SOI substrate comprising a semiconductor layer formed on a buried oxide (BOX) layer which is disposed on a semiconductor bulk substrate, forming trench isolation structures delineating a first region and a second region within the SOI substrate, removing the semiconductor layer and the BOX layer in the first region for exposing the semiconductor bulk substrate within the first region, forming a first semiconductor device with an electrode in and over the exposed semiconductor bulk substrate in the first region, forming a second semiconductor device in the second region, the second semiconductor device comprising a gate structure disposed over the semiconductor layer and the BOX layer in the second region, and performing a polishing process for defining a common height level to which the electrode and the gate structure substantially extend.

Abstract translation: 一种形成半导体器件结构的方法包括：提供具有绝缘体上半导体（SOI）结构的衬底，所述SOI衬底包括形成在半导体本体衬底上的掩埋氧化物（BOX）层上形成的半导体层，形成 描绘SOI衬底内的第一区域和第二区域的沟槽隔离结构，去除第一区域中的半导体层和BOX层，用于在第一区域内暴露半导体本体衬底，形成具有电极的第一半导体器件 在所述第一区域中暴露的半导体体基板，在所述第二区域中形成第二半导体器件，所述第二半导体器件包括设置在所述半导体层上的栅极结构和所述第二区域中的BOX层，以及执行用于定义 电极和栅极结构基本上延伸的公共高度电平。

公开(公告)号：US20160118499A1

公开(公告)日：2016-04-28

申请号：US14521939

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Peter Baars ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides in some aspects a semiconductor device and a method of forming a semiconductor device. According to some illustrative embodiments herein, the semiconductor device includes an active region formed in a semiconductor substrate, a gate structure disposed over the active region, source/drain regions formed in the active region in alignment with the gate structure, and an insulating material region buried into the active region under the gate structure, wherein the insulating material region is surrounded by the active region and borders a channel region in the active region below the gate structure along a depth direction of the active region.

Abstract translation: 本公开在一些方面提供半导体器件和形成半导体器件的方法。 根据这里的一些说明性实施例，半导体器件包括形成在半导体衬底中的有源区，设置在有源区上的栅极结构，形成在与栅极结构对准的有源区中的源/漏区，以及绝缘材料区 埋入栅极结构下的有源区，其中绝缘材料区域被有源区域包围，并且沿着有源区域的深度方向与栅极结构下方的有源区域中的沟道区域相邻。