公开(公告)号：US20140264633A1

公开(公告)日：2014-09-18

申请号：US14176767

申请日：2014-02-10

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Michael Hargrove ,  Christian Gruensfelder

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7851

Abstract: Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions.

Abstract translation: 翅片场效应晶体管器件和形成鳍式场效应晶体管器件的方法在本文中提供。 在一个实施例中，鳍状场效应晶体管器件包括具有鳍片的半导体衬底。 栅极电极结构覆盖翅片。 源极和漏极卤素和/或延伸区域和外延生长的源极区域和漏极区域形成在鳍状物中并且邻近栅电极结构设置。 体接触件设置在翅片的接触表面上，并且体接触件与卤素和/或延伸区域和外延生长的源极区域和漏极区域分开地间隔开。

公开(公告)号：US08835292B2

公开(公告)日：2014-09-16

申请号：US13664744

申请日：2012-10-31

Applicant: International Business Machines Corporation ,  Globalfoundries Inc.

Inventor： Michael P. Chudzik ,  Min Dai ,  Xiang Hu ,  Jinping Liu ,  Yanxiang Liu ,  Xiaodong Yang

IPC: H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/2807 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823462

Abstract: A method of manufacturing a semiconductor device including a replacement metal gate process incorporating a conductive dummy gate layer (e.g., silicon germanium (SiGe), titanium nitride, etc.) and a related are disclosed. The method includes forming an oxide layer on a substrate; removing a gate portion of the oxide layer from the substrate in a first region of the semiconductor device; forming a conductive dummy gate layer on the semiconductor device in the first region; and forming a gate on the semiconductor device, the gate including a gate conductor disposed in the first region and directly connected to the substrate.

Abstract translation: 公开了一种制造半导体器件的方法，该半导体器件包括结合导电虚拟栅极层（例如硅锗（SiGe），氮化钛等）的替代金属栅极工艺）和相关的方法。 该方法包括在衬底上形成氧化物层; 在所述半导体器件的第一区域中从所述衬底去除所述氧化物层的栅极部分; 在所述第一区域中的所述半导体器件上形成导电虚拟栅极层; 以及在所述半导体器件上形成栅极，所述栅极包括设置在所述第一区域中并直接连接到所述衬底的栅极导体。

公开(公告)号：US20140227845A1

公开(公告)日：2014-08-14

申请号：US13766922

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang Liu ,  Manfred Eller ,  Johannes van Meer

IPC: H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418

Abstract: One illustrative method disclosed herein involves forming an integrated circuit product comprised of first and second N-type transistors formed in and above first and second active regions, respectively. The method generally involves performing a common threshold voltage adjusting ion implantation process on the first and second active regions, forming the first and second transistors, performing an amorphization ion implantation process to selectively form regions of amorphous material in the first active region but not in the second active region, after performing the amorphization ion implantation process, forming a capping material layer above the first and second transistors and performing a re-crystallization anneal process to convert at least portions of the regions of amorphous material to a crystalline material. In some cases, the capping material layer may be formed of a material having a Young's modulus of at least 180 GPa.

Abstract translation: 本文公开的一种说明性方法涉及形成由分别形成在第一和第二活性区域中和第二活性区域上的第一和第二N型晶体管组成的集成电路产品。 该方法通常涉及对第一和第二有源区域执行公共阈值电压调整离子注入工艺，形成第一和第二晶体管，执行非晶离子注入工艺以在第一有源区域中选择性地形成非晶材料区域，但不在第 第二有源区，在执行非晶化离子注入工艺之后，在第一和第二晶体管上方形成覆盖材料层，并执行重结晶退火工艺，以将非晶材料区域的至少一部分转化为结晶材料。 在一些情况下，封盖材料层可以由杨氏模量为至少180GPa的材料形成。

公开(公告)号：US09673757B2

公开(公告)日：2017-06-06

申请号：US14156565

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L29/739 ,  H03C3/02 ,  H01L29/66 ,  H01L29/78 ,  H03C3/24 ,  H01L29/08 ,  H01L29/161

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

公开(公告)号：US09559176B2

公开(公告)日：2017-01-31

申请号：US15180312

申请日：2016-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/45 ,  H01L27/092 ,  H01L21/285 ,  H01L21/324 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US09397162B1

公开(公告)日：2016-07-19

申请号：US14679074

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peijie Feng ,  Yanxiang Liu ,  Shesh Mani Pandey ,  Jianwei Peng ,  Francis Benistant

IPC: H01L21/82 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/02 ,  H01L27/092 ,  H01L29/24

CPC classification number: H01L29/41791 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28512 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/785

Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.

Abstract translation: 公开了一种形成具有突然垂直和共形结的源极/漏极区域的方法以及所得到的器件。 实施例包括在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第一掩模; 在栅电极的每一侧上在第二极性FET的鳍的相对侧上形成间隔物，第二极性与第一极性相反; 将第一掺杂剂注入到第二极性FET的鳍中; 在栅电极的每一侧蚀刻第二极性FET的鳍的空腔; 去除第一个面罩; 进行快速热退火（RTA）; 在每个空腔中外延生长第二极性FET的源极/漏极区域; 在第一极性FET的鳍片和第一极性FET的源极/漏极区域上形成第二掩模; 以及在所述第二极性FET的源极/漏极区域中注入第二掺杂剂。

公开(公告)号：US09202911B2

公开(公告)日：2015-12-01

申请号：US13912448

申请日：2013-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure.

Abstract translation: 一个说明性器件包括形成在衬底中的源极区域和漏极区域，其中源极/漏极区域掺杂有第一类型的掺杂剂材料，位于衬底上方的栅极结构，该栅极结构横向地位于源极区域和漏极 区域和位于衬底中的漏极侧阱区域，其位于漏极区域的整个横向宽度的部分但不是全部，其中漏极侧阱区域还掺杂有第一类型的掺杂剂材料。 该器件还包括源极侧阱区域，其位于源极区域的整个宽度的整个宽度之下且在漏极区域的一部分但不是全部的位置处，并且漏极区域的延伸部分的一部分位于 部分门结构。

公开(公告)号：US20150287727A1

公开(公告)日：2015-10-08

申请号：US14742537

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/16 ,  H01L27/12

CPC classification number: H01L27/0924 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795

Abstract: Embodiments of the invention provide a semiconductor structure including a finFET having an epitaxial semiconductor region in direct physical contact with a plurality of fins, wherein the epitaxial semiconductor region traverses an insulator layer and is in direct physical contact with the semiconductor substrate. The gate of the finFET is disposed over an insulator layer, such as a buried oxide layer. Methods of forming the semiconductor structure are also included.

公开(公告)号：US09064888B2

公开(公告)日：2015-06-23

申请号：US13931211

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yanxiang Liu ,  Min-hwa Chi

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/78

Abstract: Methods for forming stacking faults in sources, or sources and drains, of TFETs to improve tunneling efficiency and the resulting devices are disclosed. Embodiments may include designating areas within a substrate that will subsequently correspond to a source region and a drain region, selectively forming a stacking fault within the substrate corresponding to the source region, and forming a tunneling field-effect transistor incorporating the source region and the drain region.

Abstract translation: 公开了用于形成TFET的源极或源极和漏极中的堆垛层错以提高隧道效率的方法以及所得到的器件。 实施例可以包括指定衬底内的区域，其随后将对应于源极区域和漏极区域，在对应于源极区域的衬底内选择性地形成堆垛层错，以及形成结合源区域和漏极的隧道场效应晶体管 地区。

公开(公告)号：US20150037945A1

公开(公告)日：2015-02-05

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.