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    Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices
    34.
    发明授权
    Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devices 有权

    公开(公告)号：US10529826B1

    公开(公告)日：2020-01-07

    申请号：US16101876

    申请日：2018-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

    IPC: H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

    Abstract: A method includes forming an active layer, forming a gate structure above a channel region of the active layer, forming a sidewall spacer adjacent the gate structure, forming a first dielectric layer adjacent the sidewall spacer, recessing the gate structure to define a gate cavity, forming an inner spacer in the gate cavity, forming a cap layer in the gate cavity, recessing the first dielectric layer and the sidewall spacer to expose sidewall surfaces of the cap layer, removing the inner spacer to define a first spacer cavity, forming an upper spacer in the spacer cavity and contacting sidewall surfaces of the cap layer, forming a second dielectric layer above the upper spacer and the cap layer, and forming a first contact structure at least partially embedded in the second dielectric layer and contacting a surface of the upper spacer.

    Gate cut in replacement metal gate process
    36.
    发明授权
    Gate cut in replacement metal gate process 有权

    公开(公告)号：US10373873B1

    公开(公告)日：2019-08-06

    申请号：US15933708

    申请日：2018-03-23

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chanro Park ,  Ruilong Xie ,  Kangguo Cheng ,  Laertis Economikos

    IPC: H01L21/8234 ,  H01L29/66

    Abstract: Gate isolation methods and structures for a FinFET device leverage the definition and formation of a gate cut opening within a sacrificial gate layer prior to patterning the sacrificial gate layer to form a sacrificial gate. The gate cut opening formed in the sacrificial gate layer is filled with a sacrificial isolation layer. After forming source/drain junctions over source/drain regions of a fin, the sacrificial isolation layer is replaced with an isolation layer, and the sacrificial gate is replaced with a functional gate.

    Self-aligned gate cut isolation
    37.
    发明授权
    Self-aligned gate cut isolation 有权

    公开(公告)号：US10366930B1

    公开(公告)日：2019-07-30

    申请号：US16005064

    申请日：2018-06-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Kangguo Cheng ,  Guillaume Bouche

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

    Abstract: A method includes forming a plurality of fins above a substrate. A first placeholder gate electrode is formed above the plurality of fins. The first placeholder gate electrode includes a placeholder material. A first sacrificial gate cut structure of a sacrificial material different than the placeholder material embedded in the first placeholder gate electrode is formed. A portion of the first placeholder gate electrode positioned above the first sacrificial gate cut structure is removed, exposing the first sacrificial gate cut structure. The first sacrificial gate cut structure is removed to define a gate cut cavity extending vertically through the first placeholder gate electrode. A dielectric material is formed in the gate cut cavity to define a gate cut structure. The first placeholder gate electrode is removed to define a first gate cavity segmented by the gate cut structure. A first replacement gate structure is formed in the first gate cavity.

    FORMING CONTACTS FOR VFETS
    38.
    发明申请
    FORMING CONTACTS FOR VFETS 审中-公开

    公开(公告)号：US20190148494A1

    公开(公告)日：2019-05-16

    申请号：US15814724

    申请日：2017-11-16

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Lars Liebmann ,  Daniel Chanemougame ,  Chanro Park ,  John H. Zhang ,  Steven Bentley ,  Hui Zang

    IPC: H01L29/10 ,  H01L29/78 ,  H01L27/24 ,  H01L21/8234

    Abstract: A first vertical field effect transistor (VFET) and a second VFET are formed on a substrate. The VFETs are parallel and adjacent to one another, and each comprises: a fin-shaped semiconductor; a lower source/drain (S/D) element; an upper S/D element; and a gate conductor. A portion of a gate conductor of the second VFET that is positioned over a lower S/D element of the second VFET is removed to leave a trench. An isolation spacer is formed to contact the gate conductor of the second VFET in a first portion of the trench. A lower S/D contact of the second VFET is formed on the lower S/D element of the second VFET in a second portion of the trench, a lower S/D contact of the first VFET is formed to a lower S/D element of the first VFET, and contacts are formed.

    Middle of the line (MOL) contacts with two-dimensional self-alignment
    39.
    发明授权
    Middle of the line (MOL) contacts with two-dimensional self-alignment 有权

    公开(公告)号：US10283408B2

    公开(公告)日：2019-05-07

    申请号：US15851774

    申请日：2017-12-22

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Lars Liebmann

    IPC: H01L29/78 ,  H01L21/768 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L29/49

    Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.

    HYBRID SPACER INTEGRATION FOR FIELD-EFFECT TRANSISTORS
    40.
    发明申请
    HYBRID SPACER INTEGRATION FOR FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20190131430A1

    公开(公告)日：2019-05-02

    申请号：US15800563

    申请日：2017-11-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Dong-Ick Lee ,  Min Gyu Sung ,  Chanro Park

    IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78

    Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.

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