公开(公告)号：US09818836B1

公开(公告)日：2017-11-14

申请号：US15486387

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Chanro Park ,  Dong-Ick Lee

IPC: H01L29/51 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a FinFET structure involves forming a gate cut within a sacrificial gate layer and backfilling the gate cut opening with etch selective dielectric materials. Partial etching of one of the dielectric materials can be used to increase the distance between the gate cut (isolation) structure and an adjacent fin relative to methods that do not perform a backfilling step using etch selective materials.

公开(公告)号：US09373696B2

公开(公告)日：2016-06-21

申请号：US14617314

申请日：2015-02-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christian Lavoie ,  Dong-Ick Lee ,  Ahmet S. Ozcan ,  Zhen Zhang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02 ,  H01L21/24 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/161

CPC classification number: H01L29/665 ,  H01L21/02381 ,  H01L21/02631 ,  H01L21/244 ,  H01L21/28518 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/161

Abstract: In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided.

公开(公告)号：US20190131430A1

公开(公告)日：2019-05-02

申请号：US15800563

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Dong-Ick Lee ,  Min Gyu Sung ,  Chanro Park

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78

Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.

公开(公告)号：US10733354B2

公开(公告)日：2020-08-04

申请号：US16225199

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hojin Kim ,  Dongyue Yang ,  Dong-Ick Lee ,  Yue Zhou ,  Jae Ho Joung ,  Gregory Costrini ,  El Mehdi Bazizi ,  Dongsuk Park

IPC: G06F30/398

Abstract: Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.

公开(公告)号：US10283617B1

公开(公告)日：2019-05-07

申请号：US15800563

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Dong-Ick Lee ,  Min Gyu Sung ,  Chanro Park

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L21/321 ,  H01L29/417 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/08 ,  H01L21/3105

Abstract: Device structures and fabrication methods for a field-effect transistor. A first dielectric spacer adjacent to a sidewall of a gate placeholder structure. A contact placeholder structure is formed adjacent to the first dielectric spacer such that the first dielectric spacer is arranged laterally between the gate placeholder structure and the contact placeholder structure. The contact placeholder structure and the first dielectric spacer are recessed to open a space over the contact placeholder structure and the first dielectric spacer. A second dielectric spacer is formed in the space adjacent to the sidewall of the gate placeholder structure and over the first dielectric spacer.