公开(公告)号：US10680085B2

公开(公告)日：2020-06-09

申请号：US15911415

申请日：2018-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/321 ,  H01L21/306 ,  H01L21/324 ,  H01L21/768

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US10658494B2

公开(公告)日：2020-05-19

申请号：US15433141

申请日：2017-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dominic J. Schepis ,  Alexander Reznicek

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49

Abstract: Devices and methods of fabricating vertical nanowires on semiconductor devices are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a first insulator disposed above the substrate, a material layer over the first insulator, a second insulator above the material layer, and a first hardmask; etching a plurality of vertical trenches through the hardmask, the first and second insulators, and the material layer; growing, epitaxially, a set of silicon nanowires from a bottom surface of the plurality of vertical trenches; etching a first set of vertical trenches to expose the material layer; etching a second set of vertical trenches to the substrate; depositing an insulating spacer material on a set of sidewalls of the first and second set of vertical trenches; and forming contacts in the first and second set of vertical trenches.

公开(公告)号：US10032870B2

公开(公告)日：2018-07-24

申请号：US14645449

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/20 ,  H01L29/16 ,  H01L21/02 ,  H01L29/36

Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

公开(公告)号：US09875939B1

公开(公告)日：2018-01-23

申请号：US15373129

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yue Ke ,  Alexander Reznicek ,  Benjamin Moser ,  Dominic J. Schepis ,  Melissa A. Smith ,  Henry K. Utomo ,  Reinaldo Vega ,  Sameer Jain

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.

公开(公告)号：US20170271483A1

公开(公告)日：2017-09-21

申请号：US15073740

申请日：2016-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dominic J. Schepis ,  Alexander Reznicek ,  Pranita Kerber ,  Qiqing C. Ouyang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/768 ,  H01L21/306 ,  H01L21/324 ,  H01L29/78 ,  H01L21/321

CPC classification number: H01L29/66818 ,  H01L21/30604 ,  H01L21/321 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Aspects of the present disclosure include finFET structures with varied cross-sectional areas and methods of forming the same. Methods according to the present disclosure can include, e.g., forming a structure including: a semiconductor fin positioned on a substrate, wherein the semiconductor fin includes: a gate area, and a terminal area laterally distal to the gate area, a sacrificial gate positioned on the gate area of the semiconductor fin, and an insulator positioned on the terminal area of the semiconductor fin; removing the sacrificial gate to expose the gate area of the semiconductor fin; increasing or reducing a cross-sectional area of the gate area of the semiconductor fin; and forming a transistor gate on the gate area of the semiconductor fin.

公开(公告)号：US09472460B1

公开(公告)日：2016-10-18

申请号：US15007494

申请日：2016-01-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alexander Reznicek ,  Kangguo Cheng ,  Ali Khakifirooz ,  Dominic J. Schepis ,  Pouya Hashemi

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/228 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/3065 ,  H01L29/785

Abstract: Methods for forming substantially uniform depth trenches and/or semiconductor fins from the trenches are disclosed. Embodiments of the method may include depositing a germanium including layer over a substrate, the substrate including a plurality of sacrificial semiconductor fins, each pair of sacrificial semiconductor fins separated by a sacrificial pillar. Germanium is diffused from the germanium including layer into the plurality of sacrificial semiconductor fins to a defined uniform depth. The germanium including layer is removed, and the plurality of sacrificial semiconductor fins are etched to the defined uniform depth and selective to the substrate, creating a plurality of trenches having a substantially uniform depth. The trenches can be used to epitaxial grow semiconductor fins having substantially uniform height.

Abstract translation: 公开了从沟槽形成基本均匀的深度沟槽和/或半导体鳍片的方法。 该方法的实施例可以包括在衬底上沉积包含锗的层，衬底包括多个牺牲半导体鳍片，每对牺牲半导体鳍片由牺牲柱分隔开。 锗从含锗层扩散到多个牺牲半导体鳍片到规定的均匀深度。 去除含锗层，并且将多个牺牲半导体散热片蚀刻到规定的均匀深度并对衬底有选择性，从而产生具有基本均匀深度的多个沟槽。 沟槽可用于外延生长具有基本均匀的高度的半导体鳍片。

公开(公告)号：US20160268378A1

公开(公告)日：2016-09-15

申请号：US14645477

申请日：2015-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8234

CPC classification number: H01L29/1054 ,  H01L21/18 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/161

Abstract: A relaxed fin and a strained fin are formed upon a semiconductor substrate. The strained fin is more highly strained relative to relaxed fin. In a particular example, the relaxed fin may be SiGe (e.g., between 20% atomic Ge concentration and 40% atomic Ge concentration, etc.) and strained fin may be SiGe (e.g., between 50% atomic Ge concentration and 80% atomic Ge concentration, etc.). The strained fin may be located in a pFET region and the relaxed fin may be located in an nFET region of a semiconductor device. As such, mobility benefits may be achieved with the strained fin in the pFET region whilst mobility liabilities may be limited with the relaxed fin in nFET region. The height of the strained fin is greater relative to a critical thickness that which growth defects occur in an epitaxially formed Si blanket layer or in an epitaxially formed Ge blanket layer.

Abstract translation: 在半导体基板上形成松弛的翅片和应变翅片。 相对于松散的翅片，应变翅片更加紧张。 在特定的例子中，松散翅片可以是SiGe（例如，在20％的原子Ge浓度和40％的原子Ge浓度之间等等），并且应变翅片可以是SiGe（例如，在50％的原子Ge浓度和80％的原子Ge之间 浓度等）。 应变鳍片可以位于pFET区域中，并且松弛鳍片可以位于半导体器件的nFET区域中。 因此，可以通过pFET区域中的应变鳍实现移动性益处，而移动性负载可以由nFET区域中的松散鳍限制。 应变翅片的高度相对于在外延形成的Si覆盖层中或在外延形成的Ge覆盖层中发生生长缺陷的临界厚度更大。

公开(公告)号：US09390925B1

公开(公告)日：2016-07-12

申请号：US14572975

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L21/00 ,  H01L21/225 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/161

Abstract: Constructing an SiGe fin by: (i) providing an intermediate sub-assembly including a silicon-containing base layer and a silicon-containing first fin structure extending in an upwards direction from the base layer; (ii) refining the sub-assembly by covering at least a portion of the top surface of the base layer and at least a portion of the first and second lateral surfaces of the first fin structure with a pre-thermal-oxidation layer that includes Silicon-Germanium (SiGe); and (iii) further refining the sub-assembly by thermally oxidizing the pre-thermal oxidation layer to migrate Ge content from the pre-thermal-oxidation layer into at least a portion of the base layer and at least a portion of first fin structure.

Abstract translation: 通过以下步骤构造SiGe翅片：（i）提供包括从基底层向上方延伸的含硅基底层和含硅的第一翅片结构的中间子组件; （ii）通过用包括硅的预热氧化层覆盖基层的顶表面的至少一部分和第一鳍结构的第一和第二侧表面的至少一部分来精炼子组件 锗（SiGe）; 和（iii）通过热氧化预热氧化层以使Ge含量从预热氧化层迁移到基层的至少一部分和第一翅片结构的至少一部分中，进一步细化子组件。

公开(公告)号：US09343550B2

公开(公告)日：2016-05-17

申请号：US14666469

申请日：2015-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/7624 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/785

Abstract: A semiconductor device includes an insulator formed within a void to electrically isolate an active fin from an underlying substrate. The void is created by removing a sacrificial portion formed between the substrate and the active fin. The sacrificial portion may be doped to allow for a greater thickness relative to an un-doped portion of substantially similar composition. The doped sacrificial portion thickness may be between 10 nm and 250 nm. The thicker sacrificial portion allows for a thicker insulator so as to provide adequate electrical isolation between the active fin and the substrate. During formation of the void, the active fin may be supported by a gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the sacrificial portion material.

Abstract translation: 半导体器件包括形成在空隙内的绝缘体，以将活性鳍与下面的衬底电隔离。 通过去除形成在衬底和活性鳍片之间的牺牲部分来产生空隙。 牺牲部分可以被掺杂以允许相对于基本相似组成的未掺杂部分具有更大的厚度。 掺杂的牺牲部分厚度可以在10nm和250nm之间。 较厚的牺牲部分允许较厚的绝缘体，以便在活性鳍片和衬底之间提供足够的电绝缘。 在形成空隙期间，活性翅片可以由浇口支撑。 半导体结构还可以包括具有牺牲部分材料的至少保持部分的主体区域。