公开(公告)号：US09741625B2

公开(公告)日：2017-08-22

申请号：US14844163

申请日：2015-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Pei-Yu Chou

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

公开(公告)号：US09466717B1

公开(公告)日：2016-10-11

申请号：US14680172

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/82 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

公开(公告)号：US09263270B2

公开(公告)日：2016-02-16

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/4763 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US20150287646A1

公开(公告)日：2015-10-08

申请号：US14244651

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括通过执行激光退火工艺来退火邻近p沟道栅叠层的半导体衬底中的卤注入区和延伸注入区。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。