公开(公告)号：US11063158B2

公开(公告)日：2021-07-13

申请号：US16716419

申请日：2019-12-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L31/02 ,  H01L31/107 ,  H01L45/00 ,  H01L31/18

Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.

公开(公告)号：US20210164845A1

公开(公告)日：2021-06-03

申请号：US16700358

申请日：2019-12-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01K7/01 ,  G11C11/406 ,  G11C7/04 ,  G11C11/4072

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

公开(公告)号：US20210159234A1

公开(公告)日：2021-05-27

申请号：US16695725

申请日：2019-11-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Xinshu Cai ,  Eng Huat Toh

IPC: H01L27/11519 ,  H01L27/11521

Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.

公开(公告)号：US10777734B2

公开(公告)日：2020-09-15

申请号：US16225005

申请日：2018-12-19

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Samarth Agarwal ,  Ruchil Kumar Jain ,  Kiok Boone Elgin Quek

IPC: G11C11/00 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

Abstract: In a non-limiting embodiment, a magnetic memory device includes a memory component having a plurality of magnetic storage elements for storing memory data, and one or more sensor components configured to detect a magnetic field external to the memory component. The sensor component outputs a signal to one or more components of the magnetic memory device based on the detected magnetic field. The memory component is configured to be terminated when the signal is above a predetermined threshold value. In some embodiments, a magnetic field is generated in a direction opposite to the direction of the detected external magnetic field when the signal is above the predetermined threshold value.

公开(公告)号：US10724983B2

公开(公告)日：2020-07-28

申请号：US16215688

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Ming Tsang Tsai ,  Khee Yong Lim ,  Kiok Boone Elgin Quek

IPC: G01N27/414

Abstract: A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.

公开(公告)号：US10553701B2

公开(公告)日：2020-02-04

申请号：US16228797

申请日：2018-12-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xueming Dexter Tan ,  Kiok Boone Elgin Quek ,  Xinfu Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L29/167

Abstract: A device and a method for forming a device are disclosed. The method includes providing a substrate prepared with a device region. A device well having second polarity type dopants is formed in the substrate. A threshold voltage (VT) implant is performed with a desired level of second polarity type dopants into the substrate. The VT implant forms a VT adjust region to obtain a desired VT of a transistor. A co-implantation with diffusion suppression material is performed to form a diffusion suppression (DS) region in the substrate. The DS region reduces or prevents segregation and out-diffusion of the VT implanted second polarity type dopants. A transistor of a first polarity type having a gate is formed in the device region. First and second diffusion regions are formed adjacent to sidewalls of the gate.

公开(公告)号：US10510859B2

公开(公告)日：2019-12-17

申请号：US16393028

申请日：2019-04-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Eng Huat Toh

IPC: H01L23/535 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L23/522 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

公开(公告)号：US10395987B2

公开(公告)日：2019-08-27

申请号：US15402150

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Chia Ching Yeo ,  Kiok Boone Elgin Quek ,  Khee Yong Lim ,  Jae Han Cha ,  Yung Fu Chong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

公开(公告)号：US10211338B2

公开(公告)日：2019-02-19

申请号：US14844522

申请日：2015-09-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L21/306 ,  H01L29/739

Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.

公开(公告)号：US09734881B2

公开(公告)日：2017-08-15

申请号：US15008475

申请日：2016-01-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Vinayak Bharat Naik ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  G11C11/15

CPC classification number: G11C11/165 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/02

Abstract: A memory device and a method for forming a memory device are disclosed. The memory device includes a memory cell having a storage unit coupled to a cell selector unit. The storage unit includes first and second storage elements. Each of the first and second storage elements includes first and second terminals. The second terminal of the first storage element is coupled to a write source line (SL-W) and the second terminal of the second storage element is coupled to a bit line (BL). The cell selector unit includes first and second selectors. The first selector includes a write select transistor (TW) and the second selector includes a first read transistor (TR1) and a second read transistor (TR2). The first selector is coupled to a word line (WL) for selectively coupling a write path to the storage unit and the second selector is coupled to a read line (RL) for selectively coupling a read path to the storage unit.