-
公开(公告)号：US08612558B2
公开(公告)日：2013-12-17
申请号：US13097584
申请日：2011-04-29
IPC分类号： G06F15/177 , G06F15/16
CPC分类号： H04L12/5692 , H04L63/0807 , H04L63/18 , H04W76/15 , H04W88/06
摘要： A connecting device discovers a first connection path to a target device and configures a first connection with the target device. The connecting device receives information about additional available connection paths from the target device via the first connection path. The connecting device automatically configures at least a second connection with the target device via an additional available connection path.
摘要翻译： 连接设备发现到目标设备的第一连接路径，并配置与目标设备的第一连接。 连接设备经由第一连接路径从目标设备接收关于附加可用连接路径的信息。 连接设备通过附加的可用连接路径自动配置与目标设备的至少第二连接。
-
公开(公告)号：US20120278452A1
公开(公告)日：2012-11-01
申请号：US13097584
申请日：2011-04-29
IPC分类号： G06F15/177
CPC分类号： H04L12/5692 , H04L63/0807 , H04L63/18 , H04W76/15 , H04W88/06
摘要： A connecting device discovers a first connection path to a target device and configures a first connection with the target device. The connecting device receives information about additional available connection paths from the target device via the first connection path. The connecting device automatically configures at least a second connection with the target device via an additional available connection path.
摘要翻译： 连接设备发现到目标设备的第一连接路径并配置与目标设备的第一连接。 连接设备经由第一连接路径从目标设备接收关于附加可用连接路径的信息。 连接设备通过附加的可用连接路径自动配置与目标设备的至少第二连接。
-
33.发明授权System and method for operating components of an integrated circuit at independent frequencies and/or voltages 有权用于在独立频率和/或电压下操作集成电路的组件的系统和方法公开(公告)号：US07263457B2
公开(公告)日：2007-08-28
申请号：US11325054
申请日：2006-01-03
IPC分类号： G01K1/08
CPC分类号： G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172
摘要： Multiple logic cores of integrated circuits and processors may be configured to operate at frequencies and voltages independently of each other. Additionally, other components, such as a common bridge configured to interface with the logic cores, may operate at a voltage and frequency independent of the voltage and frequency at which the logic cores are operating. The operating frequency and/or voltage of a logic core may be independently adjusted for various reasons, including power management and temperature control. Logic circuitry at an interface between the controller and the logic cores may translate logic signals from one voltage and/or frequency to another to enable communication between the bridge and the logic core when the two are operating at different voltages and/or frequencies.
摘要翻译： 集成电路和处理器的多个逻辑核可以被配置为在彼此独立的频率和电压下工作。 此外，其他组件，例如被配置为与逻辑内核接口的公共桥可以在与逻辑核运行的电压和频率无关的电压和频率下工作。 可以由于各种原因（包括电源管理和温度控制）独立地调整逻辑核的工作频率和/或电压。 控制器和逻辑核心之间的接口处的逻辑电路可以将逻辑信号从一个电压和/或频率转移到另一个电压和/或频率，以便当两个电路和/或频率在不同的电压和/或频率下工作时，实现桥与逻辑核之间的通信。
-
34.发明授权Electronic system and method for implementing functional redundancy checking by comparing signatures having relatively small numbers of signals 有权用于通过比较具有相对较少数量的信号的签名来实现功能冗余校验的电子系统和方法公开(公告)号：US06357024B1
公开(公告)日：2002-03-12
申请号：US09132334
申请日：1998-08-12
申请人： Drew J. Dutton , Dan S. Mudgett , Scott A. White
发明人： Drew J. Dutton , Dan S. Mudgett , Scott A. White
IPC分类号： G06F1100
CPC分类号： G06F11/1654 , G06F11/1641 , G06F11/165 , G06F2201/83
摘要： An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are “point-to-point”, enabling the processor buses to achieve relatively high data transfer rates.
摘要翻译： 通过比较由两个不同的电子设备（例如中央处理单元（CPU））产生的“签名”来呈现用于实现功能冗余检查（FRC）的电子系统和方法。 签名包括反映每个CPU的内部状态的相对较少数量的信号。 该电子系统包括第一和第二CPU。 每个CPU配置为执行指令并产生输出信号。 第一和第二CPU优选地是相同的并且同时执行指令，使得它们的内部状态和产生的输出信号在任何给定的时间应该相同。 每个CPU包括用于生成签名的签名生成器。 电子系统还包括耦合以接收签名的比较单元。 比较单元比较签名并且如果签名不相同则产生错误信号。 电子系统可以是计算机系统，还包括系统总线和芯片组逻辑。 系统总线适于耦合到一个或多个外围设备。 芯片组逻辑耦合在第一和第二CPU与系统总线之间，并且用作第一和第二CPU与系统总线之间的接口。 第一和第二CPU通过单独的处理器总线耦合到芯片组逻辑。 单独处理器总线的信号线的至少一部分是“点到点”，使得处理器总线能够实现相对较高的数据传输速率。
-
公开(公告)号：US06351801B1
公开(公告)日：2002-02-26
申请号：US09483493
申请日：2000-01-14
IPC分类号： G06F926
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.
摘要翻译： 在微处理器系统中，程序计数器电路产生表示检索到的指令的程序计数器值，并且包括用于确定下一个程序计数器值的更重要部分，较小有效部分和进位信号。 执行程序计数器电路从较不重要的程序计数器值和进位信号产生执行程序计数器值。 执行程序计数器值表示执行指令的程序计数器值。
-
36.发明授权Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead 失效测距电路，用于使用循环进位先行选择连续的重排序缓冲器序列序列
公开(公告)号：US5996067A
公开(公告)日：1999-11-30
申请号：US959158
申请日：1997-10-28
申请人： Scott A. White
发明人： Scott A. White
CPC分类号： G06F7/764 , B24B37/042 , G06F7/74 , G06F9/30018
摘要： A enable circuit (700), employing a "circular carry lookahead" technique to increase its speed performance, is provided for applying two pointers to a circular buffer--an enabling pointer (tail (218)) and a disabling pointer (head (216))--and for generating a multiple-bit enable, ENA (722) in accordance with the pointer values. The pointers designate enable bit boundaries for isolating enable bits of one logic level from enable bits of an opposite logic level. The enable circuit includes several lookahead cells (702, 704, 706 and 708) arranged in an hierarchical array, each of the cells including bits that continue the hierarchical significance. Each cell receives an hierarchical portion of the enabling pointer 218 and the disabling pointer head and a carry. From these pointers, the cell derives a generate, a propagate and the enable bits with a corresponding hierarchical significance. The propagates, generates and carries for all of the lookahead cells are interconnected using a circular propagate carry circuit (710) that provides for asserting a carry to a lookahead cell unless an intervening cell having a nonasserted propagate is interposed in the order of hierarchical significance between the cell and a cell in which enablement is generated.
摘要翻译： 提供了使用“循环进位前瞻”技术来增加其速度性能的使能电路（700），用于将两个指针应用于循环缓冲器 - 使能指针（尾部<3：0>（218））和禁用指针 （头<3：0>（216）） - 并且用于根据指针值产生多位使能ENA（722）。 指针指定使能位边界，用于将一个逻辑电平的使能位与相反逻辑电平的使能位隔离开。 使能电路包括以分层阵列布置的几个前视单元（702,704,706和708），每个单元包括继续层次重要性的位。 每个单元接收使能指针218和禁用指针头<3：0>和进位的分层部分。 从这些指针中，单元格导出生成，传播和具有相应层次重要性的使能位。 传播，产生和携带所有的前瞻性小区是使用环形传播携带电路（710）相互连接的，该环路传播携带电路（710）提供将前进小区的进位断言，除非具有非惰性传播的中间小区按照层次重要性的顺序插入 该单元和其中产生启用的单元。
-
公开(公告)号：US5799162A
公开(公告)日：1998-08-25
申请号：US716764
申请日：1996-09-23
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.
-
公开(公告)号：US5764938A
公开(公告)日：1998-06-09
申请号：US797434
申请日：1997-02-10
申请人： Scott A. White , Michael D. Goddard
发明人： Scott A. White , Michael D. Goddard
CPC分类号： G06F9/30032 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： Operations of a pipeline processor (110) are resynchronized under designated conditions. The processor updates a fetch program counter (210) and, as directed by the counter, fetches instructions from a memory (114). The processor concurrently dispatches, in the fetched order, multiple instructions to designated functional units (170, 171, 172, 173, 174 and 175). Dispatched instructions are queued in functional unit reservation stations. Result entries corresponding to the queued instructions are allocated in a reorder buffer 126 queue in their order of dispatch. Instructions are executed out of their fetched order and results are entered in the allocated result entries when execution is complete. Allocated result entries at the head of the reorder buffer queue are retired and an instruction pointer (620) is updated. The processor is resynchronized when it detects a resynchronization condition and acknowledges the resynchronization condition in the allocated result entry corresponding to the instruction that detected the condition. When the reorder buffer entry holding the resynchronization acknowledgement is retired, the processor flushes the reorder buffer and the reservation stations of the functional units and redirects the fetch program counter to the instruction addressed by the instruction pointer.
摘要翻译： 流水线处理器（110）的操作在指定条件下重新同步。 处理器更新获取程序计数器（210），并且如由计数器指示的，从存储器（114）中取出指令。 处理器以获取的顺序并发地分配指定的功能单元（170,171,172,173,174和175）的多个指令。 分派的指令在功能单元保留站中排队。 与排队指令相对应的结果条目按其分配顺序分配在重新排序缓冲器126队列中。 指令从其获取的顺序执行，并且执行完成后，结果将输入到分配的结果条目中。 在排序缓冲器队列的头部处的分配结果条目被退休，并且更新指令指针（620）。 当处理器检测到重新同步状态并确认与检测到条件的指令相对应的分配结果条目中的重新同步状态时，处理器被重新同步。 当保持重新同步确认的重新排序缓冲器条目被停止时，处理器刷新重排序缓冲器和功能单元的保留站，并将获取程序计数器重定向到由指令指针寻址的指令。
-
公开(公告)号：US5649225A
公开(公告)日：1997-07-15
申请号：US252308
申请日：1994-06-01
申请人： Scott A. White , Michael D. Goddard
发明人： Scott A. White , Michael D. Goddard
CPC分类号： G06F9/30032 , G06F9/3812 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： Operations of a pipeline processor (110) are resynchronized under designated conditions. The processor updates a fetch program counter (210) and, as directed by the counter, fetches instructions from a memory (114). The processor concurrently dispatches, in the fetched order, multiple instructions to designated functional units (170, 171, 172, 173, 174 and 175). Dispatched instructions are queued in functional unit reservation stations. Result entries corresponding to the queued instructions are allocated in a reorder buffer 126 queue in their order of dispatch. Instructions are executed out of their fetched order and results are entered in the allocated result entries when execution is complete. Allocated result entries at the head of the reorder buffer queue are retired and an instruction pointer (620) is updated. The processor is resynchronized when it detects a resynchronization condition and acknowledges the resynchronization condition in the allocated result entry corresponding to the instruction that detected the condition. When the reorder buffer entry holding the resynchronization acknowledgement is retired, the processor flushes the reorder buffer and the reservation stations of the functional units and redirects the fetch program counter to the instruction addressed by the instruction pointer.
摘要翻译： 流水线处理器（110）的操作在指定条件下重新同步。 处理器更新获取程序计数器（210），并且如由计数器指示的，从存储器（114）中取出指令。 处理器以获取的顺序并发地分配指定的功能单元（170,171,172,173,174和175）的多个指令。 分派的指令在功能单元保留站中排队。 与排队指令相对应的结果条目按其分配顺序分配在重新排序缓冲器126队列中。 指令从其获取的顺序执行，并且执行完成后，结果将输入到分配的结果条目中。 在排序缓冲器队列的头部处的分配结果条目被退休，并且更新指令指针（620）。 当处理器检测到重新同步状态并确认与检测到条件的指令相对应的分配结果条目中的重新同步状态时，处理器被重新同步。 当保持重新同步确认的重新排序缓冲器条目被停止时，处理器刷新重排序缓冲器和功能单元的保留站，并将获取程序计数器重定向到由指令指针寻址的指令。
-
公开(公告)号：US5559975A
公开(公告)日：1996-09-24
申请号：US252030
申请日：1994-06-01
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/30152 , G06F9/30174 , G06F9/321 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.
-
-
-
-
-
-
-
-
-
搜索结果
41 条记录 (耗时 0.036 秒)
