公开(公告)号：US06357024B1

公开(公告)日：2002-03-12

申请号：US09132334

申请日：1998-08-12

Applicant: Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

Inventor： Drew J. Dutton ,  Dan S. Mudgett ,  Scott A. White

IPC: G06F1100

CPC classification number: G06F11/1654 ,  G06F11/1641 ,  G06F11/165 ,  G06F2201/83

Abstract: An electronic system and method are presented for the implementation of functional redundancy checking (FRC) by comparing “signatures” produced by two different electronic devices, for example central processing units (CPUs). The signatures include a relatively small number of signals which reflect an internal state of each CPU. The electronic system includes a first and second CPU. Each CPU is configured to execute instructions and produce output signals. The first and second CPUs are preferably identical and execute instructions simultaneously such that their internal states and produced output signals should be the same at any given time. Each CPU includes a signature generator for generating the signature. The electronic system also includes a compare unit coupled to receive the signatures. The compare unit compares the signatures and produces an error signal if the signatures are not identical. The electronic system may be a computer system, further including a system bus and chip set logic. The system bus is adapted for coupling to one or more peripheral devices. The chip set logic is coupled between the first and second CPUs and the system bus, and functions as an interface between the first and second CPUs and the system bus. The first and second CPU are coupled to the chip set logic via separate processor buses. At least a portion of the signal lines of the separate processor buses are “point-to-point”, enabling the processor buses to achieve relatively high data transfer rates.

Abstract translation: 通过比较由两个不同的电子设备（例如中央处理单元（CPU））产生的“签名”来呈现用于实现功能冗余检查（FRC）的电子系统和方法。 签名包括反映每个CPU的内部状态的相对较少数量的信号。 该电子系统包括第一和第二CPU。 每个CPU配置为执行指令并产生输出信号。 第一和第二CPU优选地是相同的并且同时执行指令，使得它们的内部状态和产生的输出信号在任何给定的时间应该相同。 每个CPU包括用于生成签名的签名生成器。 电子系统还包括耦合以接收签名的比较单元。 比较单元比较签名并且如果签名不相同则产生错误信号。 电子系统可以是计算机系统，还包括系统总线和芯片组逻辑。 系统总线适于耦合到一个或多个外围设备。 芯片组逻辑耦合在第一和第二CPU与系统总线之间，并且用作第一和第二CPU与系统总线之间的接口。 第一和第二CPU通过单独的处理器总线耦合到芯片组逻辑。 单独处理器总线的信号线的至少一部分是“点到点”，使得处理器总线能够实现相对较高的数据传输速率。

公开(公告)号：US08239603B2

公开(公告)日：2012-08-07

申请号：US11417391

申请日：2006-05-03

Applicant: Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

Inventor： Drew J. Dutton ,  Alan D. Berenbaum ,  Raphael Weiss

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Abstract translation: 一种包括序列化二次总线架构的系统。 该系统可以包括LPC总线，I / O控制器，串行化辅助总线和至少一个从设备。 LPC总线可以连接到I / O控制器，并且至少一个从设备可以经由串行辅助总线连接到I / O控制器。 串行次级总线相对于LPC总线的引脚数量减少。 I / O控制器可以从LPC总线接收总线事务。 I / O控制器可以通过辅助总线将LPC总线事务转换和转发到至少一个设备。 I / O控制器可以包括处理单元。 处理单元可以启动用于至少一个从设备的总线事务。 I / O控制器还可以包括总线仲裁单元。 总线仲裁单元可以仲裁处理单元和LPC总线之间的辅助总线的所有权。

公开(公告)号：US6047350A

公开(公告)日：2000-04-04

申请号：US989329

申请日：1997-12-11

Applicant: Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

Inventor： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

IPC: G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

CPC classification number: H04N21/238 ,  G06F13/36 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4027

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

Abstract translation: 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到一个或多个扩展总线和/或多媒体总线的字节分片逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片多媒体总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5923887A

公开(公告)日：1999-07-13

申请号：US650570

申请日：1996-05-20

Applicant: Drew J. Dutton

Inventor： Drew J. Dutton

IPC: G06F13/24 ,  G06F9/46

CPC classification number: G06F13/24

Abstract: An improved programmable interrupt controller for use in a computer system including one or more interrupt service providers (ISPs), usually central processing units (CPUs). At least one CPU and a main memory system are coupled to a host bus. A bus bridge device couples the host bus to the expansion bus. At least one I/O device is coupled to the expansion bus and generates an interrupt request signal. The bus bridge and other bus devices may also generate interrupt request signals. A programmable interrupt controller receives the interrupt requests and provides processor interrupt signals as well as information regarding resource requirements necessary for servicing the interrupts to the one or more CPUs. The programmable interrupt controller also receives interrupt acknowledge signals from the one or more CPUs.

Abstract translation: 一种改进的可编程中断控制器，用于包括一个或多个中断服务提供商（ISP）的计算机系统，通常是中央处理单元（CPU）。 至少一个CPU和主存储器系统耦合到主机总线。 总线桥装置将主机总线耦合到扩展总线。 至少一个I / O设备被耦合到扩展总线并产生中断请求信号。 总线桥和其他总线设备也可能产生中断请求信号。 可编程中断控制器接收中断请求并提供处理器中断信号以及关于维护一个或多个CPU的中断所需的资源需求的信息。 可编程中断控制器还从一个或多个CPU接收中断确认信号。

公开(公告)号：US5819080A

公开(公告)日：1998-10-06

申请号：US582125

申请日：1996-01-02

Applicant: Drew J. Dutton ,  David S. Christie

Inventor： Drew J. Dutton ,  David S. Christie

IPC: G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F9/30094 ,  G06F12/0804 ,  G06F12/0888 ,  G06F9/30185 ,  G06F9/383 ,  G06F9/3846

Abstract: A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction. Branch instructions may be scheduled distant from the instruction which sets the condition flags tested by the branch instruction. Numerous instructions may be placed between the two instructions, such that the condition flags may be available at the time the instruction is fetched. The branch instruction may be executed without stalling until the condition flags are available. In another embodiment, the branch prediction unit is configured to predict the direction a branch instruction may take according to a branch prediction scheme. Additionally, upon detection of a segment override prefix byte, the branch prediction unit uses an alternative branch prediction scheme. The alternative branch prediction scheme may be to predict the branch taken if a particular segment register override prefix byte is detected, and to predict the branch not taken if another particular segment register override prefix byte is detected.

Abstract translation: 提供了一种微处理器，其包括分支预测单元，该分支预测单元被配置为根据可能包含在该指令中的分段寄存器覆盖前缀字节来选择由分支指令使用的多组条件标志中的一个。 分支指令可以被调度为远离设置由分支指令测试的条件标志的指令。 可以在两个指令之间放置许多指令，使得条件标志在获取指令时可用。 分支指令可以在不停止的情况下执行，直到条件标志可用。 在另一实施例中，分支预测单元被配置为根据分支预测方案来预测分支指令可以采用的方向。 此外，在检测到段重写前缀字节时，分支预测单元使用替代分支预测方案。 替代分支预测方案可以是预测如果检测到特定分段寄存器覆盖前缀字节所采取的分支，并且如果检测到另一个特定分段寄存器覆盖前缀字节，则预测未采用的分支。

公开(公告)号：US5317715A

公开(公告)日：1994-05-31

申请号：US911783

申请日：1992-07-10

Applicant: William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

Inventor： William M. Johnson ,  Timothy A. Olson ,  Drew J. Dutton ,  Sherman Lee ,  David W. Stoenner

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/00 ,  G06F13/23

CPC classification number: G06F13/4013 ,  G06F13/28

Abstract: Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Abstract translation: 公开了用于向简化指令集计算机（RISC）系统的本地总线传输数据的方法和装置，包括至少一个中央处理器（“CPU”）的第一组高性能设备， 和远程总线，第二组相对较低性能的设备以不限制RISC处理器性能的方式连接到该远程总线。 根据本发明的优选实施例，公开了一种RISC架构，其包括新颖的数据传输控制器（“DTC”）或一组DTC，适用于在高性能本地总线与一个或多个本地总线之间执行上述数据传输功能 通常具有不同（和较低）性能特征的完整子系统或外设的远程总线。 由此产生的RISC节点允许商业化的外围设备和子系统与高性能RISC处理器配合使用，而不会限制RISC系统的性能。

公开(公告)号：US08149001B2

公开(公告)日：2012-04-03

申请号：US12359056

申请日：2009-01-23

Applicant: Simeon K. Iliev ,  Drew J. Dutton

Inventor： Simeon K. Iliev ,  Drew J. Dutton

IPC: G01R27/26

CPC classification number: G06K9/0002

Abstract: Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

Abstract translation: 具有单芯片解决方案的低成本指纹系统包括电路板，制造在电路板的第一表面上的指纹传感器阵列和用于处理从指纹传感器阵列接收的信息的集成电路管芯直接安装在第二表面 电路板。 集成电路管芯可以通过例如电路板中的通孔电连接到传感器。

公开(公告)号：US07685450B2

公开(公告)日：2010-03-23

申请号：US11674450

申请日：2007-02-13

Applicant: Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

Inventor： Drew J. Dutton ,  James R. MacDonald ,  Stephen Cox

IPC: G06F1/00

CPC classification number: G06F1/3215

Abstract: A system and method for monitoring usage of peripheral devices and placing a second peripheral device in a low power state when the usage indicates that a second peripheral device is not being used. For example, if a computer system detects that a user's current typing rate indicates the user probably has both hands on a keyboard, the computer system may generate a signal to the computer mouse to enter a low power state. The computer system may use prior usage for a user to determine when current usage indicates that the second peripheral device is not being used. After the second peripheral device is placed in a low power state, the computer system may generate a signal to the second peripheral device to return to a normal power state when the computer system determines that the user no longer has both hands occupied.

Abstract translation: 一种用于监视外围设备的使用并且当使用指示没有使用第二外围设备时将第二外围设备置于低功率状态的系统和方法。 例如，如果计算机系统检测到用户的当前打字率指示用户可能在键盘上具有双手，则计算机系统可以向计算机鼠标生成信号以进入低功率状态。 计算机系统可以使用用户的先前使用来确定当前使用情况何时指示第二外围设备未被使用。 在第二外围设备处于低功率状态之后，当计算机系统确定用户不再具有双手时，计算机系统可以向第二外围设备产生信号以返回到正常的功率状态。

公开(公告)号：US20100039121A1

公开(公告)日：2010-02-18

申请号：US12359056

申请日：2009-01-23

Applicant: Simeon K. Iliev ,  Drew J. Dutton

Inventor： Simeon K. Iliev ,  Drew J. Dutton

IPC: G01R27/26 ,  G06F15/00

CPC classification number: G06K9/0002

Abstract: Low cost fingerprint system having a single chip solution includes a circuit board, a fingerprint sensor array fabricated onto a first surface of the circuit board, and an integrated circuit die for processing information received from the fingerprint sensor array is mounted directly to a second surface of the circuit board. The integrated circuit die may be electrically connected to the sensor by, for example, vias in the circuit board.

Abstract translation: 具有单芯片解决方案的低成本指纹系统包括电路板，制造在电路板的第一表面上的指纹传感器阵列和用于处理从指纹传感器阵列接收的信息的集成电路管芯直接安装在第二表面 电路板。 集成电路管芯可以通过例如电路板中的通孔电连接到传感器。

公开(公告)号：US06825786B1

公开(公告)日：2004-11-30

申请号：US10430863

申请日：2003-05-06

Applicant: James R. MacDonald ,  Drew J. Dutton ,  Stephen Cox

Inventor： James R. MacDonald ,  Drew J. Dutton ,  Stephen Cox

IPC: H03M166

CPC classification number: G10K11/178 ,  G10K2210/11 ,  G10K2210/3033 ,  G11B20/10009

Abstract: A system may include a memory configured to store an attenuation waveform and control logic. The control logic is configured to receive a synchronizing signal indicative of an operating characteristic of a noise source. In response to a value of a characteristic (e.g., frequency) of the synchronizing signal, the control logic is configured to output the attenuation waveform from the memory if the attenuation waveform is associated with that value of the characteristic of the synchronizing signal. An attenuating noise generated dependent on the attenuation waveform attenuates a noise generated by the noise source.

Abstract translation: 系统可以包括被配置为存储衰减波形和控制逻辑的存储器。 控制逻辑被配置为接收指示噪声源的操作特性的同步信号。 响应于同步信号的特性（例如，频率）的值，如果衰减波形与同步信号的特性值相关联，则控制逻辑被配置为从存储器输出衰减波形。 根据衰减波形产生的衰减噪声会衰减由噪声源产生的噪声。