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公开(公告)号：US06792508B1
公开(公告)日：2004-09-14
申请号：US09591656
申请日：2000-06-09
IPC分类号： G06F1208
CPC分类号： G06F12/0802 , G06F12/0862 , G06F12/0864 , G06F12/0895 , G06F2212/1016 , G06F2212/2515
摘要： A cache architecture (16) for use in a processing device includes a RAM set cache for caching a contiguous block of main memory (20). The RAM set cache can be used in conjunction with other cache types, such as a set associative cache or a direct mapped cache. A register (32) define a starting address for the contiguous block of main memory (20). The data array (38) associated with the RAM set may be filled on a line by line basis, as lines are requested by the processing core, or on a set-fill basis which fills the data array (38) when the starting address is loaded into the register (32). As addresses are received from the processing core hit miss logic (46) the starting address register (32), a global valid bit (34), line valid bits (37) and control bits (24, 26) are used to determine whether the data is present in the RAM set or whether the data must be loaded from main memory (20). The hit/miss logic (46) also determines whether a line should be loaded into the RAM set data array (38) or in the associated cache.
摘要翻译： 用于处理设备的高速缓存结构（16）包括用于缓存主存储器（20）的连续块的RAM组高速缓存。 RAM集缓存可以与其他缓存类型一起使用，例如集合关联高速缓存或直接映射高速缓存。 寄存器（32）定义主存储器（20）的连续块的起始地址。 与RAM组相关联的数据阵列（38）可以逐行地填充，因为处理核心要求线路，或者填充数据阵列（38）时的起始地址为 加载到寄存器（32）中。 由于从处理核心命中漏错逻辑（46）接收到地址，起始地址寄存器（32），全局有效位（34），行有效位（37）和控制位（24,26）用于确定是否 数据存在于RAM集合中，或者数据是否必须从主存储器（20）加载。 命中/未命中逻辑（46）还确定是否将线路加载到RAM集数据阵列（38）或相关联的高速缓存中。
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32.发明授权Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field 有权快速硬件循环机制，用于缓存清理和刷新对应于限定符字段的缓存条目公开(公告)号：US06766421B2
公开(公告)日：2004-07-20
申请号：US09932363
申请日：2001-08-17
申请人： Serge Lasserre , Gerard Chauvel
发明人： Serge Lasserre , Gerard Chauvel
IPC分类号： G06F1200
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F11/3409 , G06F12/0802 , G06F12/0891 , G06F12/1081 , G06F2201/81 , G06F2201/815 , G06F2201/88 , G06F2201/885 , G06F2212/1028 , G06F2212/681 , Y02D10/13 , Y02D10/24
摘要： A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity with corresponding tag arrays (502(n)), four segments per entry and four valid and dirty bits. Each tag entry (1236) includes task-ID qualifier field (522) and a resource ID qualifier field (520). Data is loaded into various of lines (506) in the cache in response to cache access requests when a given cache access request misses. After loading data into the cache in response to a miss, a tag (1236) associated with the data line is set to a valid state (526). In addition to setting a tag to a valid state, qualifier values are stored in qualifier fields (520, 522) in the tag. Each qualifier value specifies a usage characteristic of data stored in an associated data line of the cache. In response to an operation command (1251), each tag in the array of tags that contains a specified qualifier value is modified (1258) in accordance with the operation command. Various types of operation commands can be included in an embodiment of the invention, such as clean, flush, clean-flush, lock, and unlock, for example.
摘要翻译： 数字系统具有几个处理器，与每个处理器相关联的私有一级（L1）高速缓存，每个条目具有多个段的共享二级（L2）高速缓存以及三级（L3）物理存储器。 共享的L2高速缓存架构体现为与相应的标签阵列（502（n）），每个条目四个段和四个有效位和脏位的四路关联性。 每个标签条目（1236）包括任务ID限定符字段（522）和资源ID限定字段（520）。 当给定的高速缓存访问请求未命中时，响应于高速缓存访问请求，将数据加载到高速缓存中的各种行（506）中。 响应于未命中将数据加载到高速缓存中之后，将与数据线相关联的标签（1236）设置为有效状态（526）。 除了将标签设置为有效状态之外，限定符值存储在标签中的限定符字段（520,522）中。 每个限定符值指定存储在高速缓存的关联数据行中的数据的使用特性。 响应于操作命令（1251），根据操作命令修改（1258）包含指定限定符值的标签阵列中的每个标签。 例如，可以在本发明的实施例中包括各种类型的操作命令，例如清洁，冲洗，清洁冲洗，锁定和解锁。
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33.发明授权公开(公告)号：US06742104B2
公开(公告)日：2004-05-25
申请号：US09932607
申请日：2001-08-17
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F12/1027 , G06F12/1081 , G06F2212/681 , G06F2212/684 , Y02D10/13
摘要： A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.
摘要翻译： 多处理器系统（20,102,110）使用多个操作系统，或者单个操作系统使用muTLB（36）和共享TLB子系统（48）来提供虚拟地址到物理地址的有效和灵活的转换。 在muTLB和共享TLB中缺失时，可以使用硬件机制（100）或软件功能来访问外部存储器（54）中的翻译表。 可以基于诸如资源标识符和任务标识符的多个标准来灵活地进行翻译。 诸如协处理器（34）和DMA处理器（24）之类的从属处理器可以在没有主处理器交互的情况下访问共享的TLB 48，以便更有效的操作。
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公开(公告)号：US06742103B2
公开(公告)日：2004-05-25
申请号：US09932362
申请日：2001-08-17
IPC分类号： G06F1208
CPC分类号： G06F12/1036 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5011 , G06F12/1081 , G06F2212/681 , Y02D10/24
摘要： A multiprocessor system (20, 102, 110) uses multiple operating systems or a single operating system uses &mgr;TLBs (36) and a shared TLB subsystem (48) to provide efficient and flexible translation of virtual addresses to physical addresses. Upon misses in the &mgr;TLB and shared TLB, access to a translation table in external memory (54) can be made using either a hardware mechanism (100) or a software function. The translation can be flexibly based on a number of criteria, such as a resource identifier and a task identifier. Slave processors, such as coprocessors (34) and DMA processors (24) can access the shared TLB 48 without master processor interaction for more efficient operation.
摘要翻译： 多处理器系统（20,102,110）使用多个操作系统，或者单个操作系统使用muTLB（36）和共享TLB子系统（48）来提供虚拟地址到物理地址的有效和灵活的转换。 在muTLB和共享TLB中缺失时，可以使用硬件机制（100）或软件功能来访问外部存储器（54）中的翻译表。 可以基于诸如资源标识符和任务标识符的多个标准来灵活地进行翻译。 诸如协处理器（34）和DMA处理器（24）之类的从属处理器可以在没有主处理器交互的情况下访问共享的TLB 48，以便更有效的操作。
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公开(公告)号：US06684280B2
公开(公告)日：2004-01-27
申请号：US09932380
申请日：2001-08-17
申请人： Gerard Chauvel , Serge Lasserre
发明人： Gerard Chauvel , Serge Lasserre
IPC分类号： G06F1300
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F12/0891 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2212/1028 , Y02D10/13 , Y02D10/24
摘要： A digital system and method of operation is provided in which several processors (1400, 1402, 1404) are connected to a shared resource (1432). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register. The arbitration circuitry is operable to schedule access to the shared resource according to the access priority values provided by the processors. A software priority state is established during execution of an instruction module on each of the several processors. An instruction is executed on each processor to form an access request to the shared resource. An access priority value is provided with each access request that is responsive to the software priority state of the respective processor. The sequence of instructions is part of a task and the software state is established by defining a task priority for the task and setting the software state in accordance with the task priority. The software priority state is saved during a context switch.
摘要翻译： 提供了一种数字系统和操作方法，其中多个处理器（1400,1402,1404）连接到共享资源（1432）。 每个处理器具有通过在处理器上执行的软件加载访问优先级值的访问优先级寄存器（1410）。 仲裁电路（1430）被连接以从每个访问优先级寄存器接收来自每个处理器的请求信号以及访问优先级值。 仲裁电路可操作以根据由处理器提供的访问优先级值来调度对共享资源的访问。 在执行多个处理器中的每个处理器上的指令模块时建立软件优先级状态。 在每个处理器上执行指令以形成对共享资源的访问请求。 提供访问优先级值，每个访问请求响应于相应处理器的软件优先级状态。 指令序列是任务的一部分，通过为任务定义任务优先级并根据任务优先级设置软件状态来建立软件状态。 在上下文切换期间保存软件优先级状态。
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公开(公告)号：US06606687B1
公开(公告)日：2003-08-12
申请号：US09447194
申请日：1999-11-22
IPC分类号： G06F1200
CPC分类号： G06F12/0804
摘要： A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During the hardware clean function, the MAX counter (82) counts downward while cache entries at the address given by the MAX counter (82) are written to main memory (16) if the entry is marked as dirty. If an interrupt occurs, the MAX counter is disabled until a subsequent clean request is issued after the interrupt is serviced.
摘要翻译： VIVT（虚拟索引，虚拟标签）缓存（18）使用可中断的硬件清理功能来清除上下文切换期间高速缓存中的脏条目。 MAX计数器（82）和MIN寄存器（84）定义了脏的高速缓存位置的范围。 在硬件清理功能期间，如果条目被标记为脏，则MAX计数器（82）向下计数，而由MAX计数器（82）给出的地址处的缓存条目被写入主存储器（16）。 如果发生中断，则在中断服务完成之后，MAX计数器将被禁止，直到发出后续清除请求。
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37.发明授权公开(公告)号：US08539159B2
公开(公告)日：2013-09-17
申请号：US10631185
申请日：2003-07-31
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F2212/502
摘要： Methods and apparatuses are disclosed for managing memory write back. In some embodiments, the method may include examining current and future instructions operating on a stack that exists in memory, determining stack trend information from the instructions, and utilizing the trend information to reduce data traffic between various levels of the memory. As stacked data are written to a cache line in a first level of memory, if future instructions indicate that additional cache lines are required for subsequent write operations within the stack, then the cache line may be written back to a second level of memory. If however, the future instructions indicate that no additional cache lines are required for subsequent write operations within the stack, then the first level of memory may avoid writing back the cache line and also may keep it marked as dirty.
摘要翻译： 公开了用于管理存储器回写的方法和装置。 在一些实施例中，该方法可以包括检查在存储器中存在的堆栈上操作的当前和未来指令，从指令确定堆栈趋势信息，以及利用趋势信息来减少存储器的各个级别之间的数据流量。 当堆叠数据被写入第一级存储器中的高速缓存行时，如果未来的指令指示需要额外的高速缓存行用于堆栈内的后续写入操作，则高速缓存行可以被写回到第二级存储器。 然而，如果未来的指令指示不需要额外的高速缓存行用于堆栈内的后续写入操作，则第一级存储器可以避免写回高速缓存行并且还可以将其标记为脏。
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公开(公告)号：US08032891B2
公开(公告)日：2011-10-04
申请号：US10151282
申请日：2002-05-20
申请人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
发明人： Gerard Chauvel , Dominique D'Inverno , Serge Lasserre , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Frédéric Parain , Jean-Paul Routeau , Salam Majoul
CPC分类号： G06F9/4881 , G06F1/3228 , G06F1/329 , Y02D10/24
摘要： A mobile device (10) manages tasks (18) using a scheduler (20) for scheduling tasks on multiple processors (12). To conserve energy, the set of tasks to be scheduled are divided into two (or more) subsets, which are scheduled according to different procedures. In a specific embodiment, the first subset contains tasks with the highest energy consumption deviation based on the processor that executes the task. This subset is scheduled according to a power-aware procedure for scheduling tasks primarily based on energy consumption criteria. If there is no failure, the second subset is scheduled according to a real-time constrained procedure that schedules tasks primarily based on the deadlines associated with the various tasks in the second subset. If there is a failure in either procedure, one or more tasks with the lowest energy consumption deviation are moved from the first subset to the second subset and the scheduling is repeated.
摘要翻译： 移动设备（10）使用调度器（20）管理任务（18），用于在多个处理器（12）上调度任务。 为了节约能源，要调度的任务集合分为两个（或多个）子集，根据不同的过程进行调度。 在具体实施例中，第一子集基于执行任务的处理器包含具有最高能量消耗偏差的任务。 该子集根据用于主要基于能量消耗标准的调度任务的功率感知程序进行调度。 如果没有失败，则根据实时约束程序调度第二子集，该实时约束过程主要基于与第二子集中的各种任务相关联的期限来调度任务。 如果任何一个过程都有故障，则能量消耗偏差最小的一个或多个任务从第一个子集移动到第二个子集，重复调度。
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公开(公告)号：US07941790B2
公开(公告)日：2011-05-10
申请号：US10003570
申请日：2001-10-24
申请人： Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Gerard Chauvel , Dominique D'Inverno , Teresa Higuera , Valerie Issarny , Serge Lasserre , Frederic Parain , Jean-Paul Routeau
发明人： Gilbert Cabillic , Jean-Philippe Lesot , Michel Banatre , Gerard Chauvel , Dominique D'Inverno , Teresa Higuera , Valerie Issarny , Serge Lasserre , Frederic Parain , Jean-Paul Routeau
IPC分类号： G06F9/45
摘要： A method for generating program code for translating high level code into instructions for one of a plurality of target processors comprises first determining a desired program code characteristic corresponding to a target processor. Then, selecting one or more predefined program code modules from a plurality of available program code modules in accordance with said desired program code characteristic, and generating program code for translating high level code into instructions for said target processor from said selected one or more predefined program code modules. Preferably, the method comprises forming agglomerated program code from a plurality of program code modules in accordance with said desired program code characteristic.
摘要翻译： 一种用于产生用于将高级代码转换为多个目标处理器之一的指令的程序代码的方法包括首先确定与目标处理器相对应的期望的程序代码特性。 然后，根据所述期望的程序代码特征从多个可用的程序代码模块中选择一个或多个预定义的程序代码模块，以及生成用于将所述目标处理器从所述选定的一个或多个预定程序转换成指令的程序代码 代码模块 优选地，该方法包括根据所述期望的程序代码特征从多个程序代码模块形成聚集的程序代码。
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公开(公告)号：US07840782B2
公开(公告)日：2010-11-23
申请号：US10631308
申请日：2003-07-31
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/30174 , G06F9/3879 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502 , Y02D10/13
摘要： A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance with at least some embodiments of the invention, the processor may comprise a multi-entry stack usable in at least a stack-based instruction set, logic coupled to and managing the stack, and a plurality of registers coupled to the logic and addressable through a second instruction set that provides register-based and memory-based operations.
摘要翻译： 尽管在本公开的范围内不需要代码加速，处理器（例如，协处理器）以加速基于堆栈的指令集的执行的方式执行基于堆栈的指令集和另一指令。 根据本发明的至少一些实施例，处理器可以包括可用于至少基于堆栈的指令集，耦合到和管理堆栈的逻辑的多入栈，以及耦合到逻辑和可寻址的多个寄存器 通过提供基于寄存器和基于存储器的操作的第二指令集。
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