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31.发明授权Programming and erasing structure for a floating gate memory cell and method of making 有权浮动存储单元的编程和擦除结构及其制作方法公开(公告)号：US07183161B2
公开(公告)日：2007-02-27
申请号：US10944244
申请日：2004-09-17
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate memory cell has a floating gate in which there are two floating gate layers. The top layer is etched to provide a contour in the top layer while leaving the lower layer unchanged. The control gate follows the contour of the floating gate to increase capacitance therebetween. The two layers of the floating gate can be polysilicon separated by a very thin etch stop layer. This etch stop layer is thick enough to provide an etch stop during a polysilicon etch but preferably thin enough to be electrically transparent. Electrons are able to easily move between the two layers. Thus the etch of the top layer does not extend into the lower layer but the first and second layer have the electrical effect for the purposes of a floating gate of being a continuous conductive layer.
摘要翻译： 浮动栅极存储单元具有浮置栅极，其中存在两个浮置栅极层。 蚀刻顶层以在顶层中提供轮廓，同时保持下层不变。 控制栅极跟随浮动栅极的轮廓以增加它们之间的电容。 浮置栅极的两层可以是由非常薄的蚀刻停止层分离的多晶硅。 该蚀刻停止层足够厚以在多晶硅蚀刻期间提供蚀刻停止，但优选足够薄以使其具有电透明性。 电子能够容易地在两层之间移动。 因此，顶层的蚀刻不延伸到下层，但是为了作为连续导电层的浮动栅极的目的，第一和第二层具有电效应。
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公开(公告)号：US20070020857A1
公开(公告)日：2007-01-25
申请号：US11188939
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/7624 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/42344 , H01L29/42348 , H01L29/42352 , Y10S977/707
摘要： A process for forming an electronic device can include forming a first trench within a substrate, wherein the trench includes a wall and a bottom and extends from a primary surface of the substrate. The process can also include forming discontinuous storage elements and forming a first gate electrode within the trench such that, a first discontinuous storage element of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The process can further include removing the discontinuous storage elements that overlie the primary surface of the substrate. The process can still further include forming a second gate electrode that overlies the first gate electrode and the primary surface of the substrate.
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33.发明授权公开(公告)号：US07550348B2
公开(公告)日：2009-06-23
申请号：US11536190
申请日：2006-09-28
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.
摘要翻译： 存储装置结构（10）每个控制栅极（34）具有两位存储，并且使用源极侧注入（SSI）来提供较低的编程电流。 控制栅极（34）覆盖由位于半导体衬底（12）中的掺杂区域（22）形成的漏电极。 两个选择栅极（49和50）被实现为与控制栅极（34）相邻并在其侧面的导电侧壁间隔件。 源极掺杂区域（60）位于与选择栅极之一相邻的半导体衬底（12）中，用于提供要注入到控制栅极下面的存储层（42）中的电子源。 存在来自编程的SSI方法的较低编程结果和紧凑的存储单元尺寸。
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34.发明授权公开(公告)号：US07235823B2
公开(公告)日：2007-06-26
申请号：US11536099
申请日：2006-09-28
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.
摘要翻译： 存储装置结构（10）每个控制栅极（34）具有两位存储，并且使用源极侧注入（SSI）来提供较低的编程电流。 控制栅极（34）覆盖由位于半导体衬底（12）中的掺杂区域（22）形成的漏电极。 两个选择栅极（49和50）被实现为与控制栅极（34）相邻并在其侧面的导电侧壁间隔件。 源极掺杂区域（60）位于与选择栅极之一相邻的半导体衬底（12）中，用于提供要注入到控制栅极下面的存储层（42）中的电子源。 存在来自编程的SSI方法的较低编程结果和紧凑的存储单元尺寸。
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35.发明授权Source side injection storage device with control gates adjacent to shared source/drain and method therefor 有权源侧注入存储装置，具有与共享源极/漏极相邻的控制栅极及其方法公开(公告)号：US07378314B2
公开(公告)日：2008-05-27
申请号：US11170446
申请日：2005-06-29
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42328 , H01L29/42332 , H01L29/66545 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： A storage device has a two bit cell in which the select electrode is nearest the channel between two storage layers. Individual control electrodes are over individual storage layers. Adjacent cells are separated by a doped region that is shared between the adjacent cells. The doped region is formed by an implant in which the select gates of adjacent cells are used as a mask. This structure provides for reduced area while retaining the ability to perform programming by source side injection.
摘要翻译： 存储设备具有两位单元，其中选择电极最靠近两个存储层之间的通道。 单独的控制电极在单独的存储层之上。 相邻的细胞由在相邻细胞之间共享的掺杂区域分离。 掺杂区域由其中相邻单元的选择栅极用作掩模的注入形成。 该结构提供了减小的面积，同时保留了通过源侧注入执行编程的能力。
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36.发明授权Electronic device including discontinuous storage elements and a process for forming the same 有权包括不连续存储元件的电子设备及其形成方法公开(公告)号：US07256454B2
公开(公告)日：2007-08-14
申请号：US11188953
申请日：2005-07-25
IPC分类号： H01L29/423
CPC分类号： H01L29/7887 , B82Y10/00 , G11C16/0458 , G11C16/0475 , G11C16/0491 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42348 , H01L29/42352 , H01L29/7923 , H01L29/7926
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 在一个实施例中，电子设备可以包括包括延伸到半导体材料中的沟槽的衬底。 沟槽可以包括凸缘和底部，其中底部位于比凸缘更深的深度。 电子设备可以包括不连续的存储元件，其中不连续存储元件的沟槽部分位于沟槽内。 栅电极可以邻近沟槽的壁。 在特定实施例中，存储器单元内的通道区域的一部分可能不被栅电极覆盖。 在另一个实施例中，掺杂区域可以在凸缘的下面，并允许在沟槽内的不同高度处形成存储单元。 在其他实施例中，可以使用一种工艺来形成电子设备。
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37.发明授权公开(公告)号：US07132329B1
公开(公告)日：2006-11-07
申请号：US11170447
申请日：2005-06-29
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7923
摘要： A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.
摘要翻译： 存储装置结构（10）每个控制栅极（34）具有两位存储，并且使用源极侧注入（SSI）来提供较低的编程电流。 控制栅极（34）覆盖由位于半导体衬底（12）中的掺杂区域（22）形成的漏电极。 两个选择栅极（49和50）被实现为与控制栅极（34）相邻并在其侧面的导电侧壁间隔件。 源极掺杂区域（60）位于与选择栅极之一相邻的半导体衬底（12）中，用于提供要注入到控制栅极下面的存储层（42）中的电子源。 存在来自编程的SSI方法的较低编程结果和紧凑的存储单元尺寸。
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38.发明授权公开(公告)号：US09111908B2
公开(公告)日：2015-08-18
申请号：US13448531
申请日：2012-04-17
IPC分类号： H01L29/76 , H01L29/423 , H01L21/28 , H01L27/115 , H01L29/788
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/7881
摘要： Embodiments include a split-gate non-volatile memory cell that is formed having a control gate and a select gate, where at least a portion of the control gate is formed over the select gate. A charge storage layer is formed between the select gate and the control gate. The select gate is formed using a first conductive layer and a second conductive layer. The second conductive layer is formed over the first conductive layer and has a lower resistivity than the first conductive layer. In one embodiment, the first conductive layer is polysilicon and the second conductive layer is titanium nitride (TiN). In another embodiment, the second conductive layer may be a silicide or other conductive material, or combination of conductive materials having a lower resistivity than the first conductive layer.
摘要翻译： 实施例包括形成为具有控制栅极和选择栅极的分离栅极非易失性存储器单元，其中控制栅极的至少一部分形成在选择栅极上。 在选择栅极和控制栅极之间形成电荷存储层。 选择栅极使用第一导电层和第二导电层形成。 第二导电层形成在第一导电层之上，并且具有比第一导电层更低的电阻率。 在一个实施例中，第一导电层是多晶硅，第二导电层是氮化钛（TiN）。 在另一个实施例中，第二导电层可以是硅化物或其它导电材料，或者具有比第一导电层低的电阻率的导电材料的组合。
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公开(公告)号：US08173505B2
公开(公告)日：2012-05-08
申请号：US12254331
申请日：2008-10-20
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L27/11526 , H01L27/11536 , H01L27/11543 , H01L27/11573 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gate material over the charge storage layer; removing a portion of the second layer and a portion of the charge storage layer which overlie the hard mask layer, wherein a second portion of the second layer remains within the opening; forming a patterned masking layer over the hard mask layer and over the second portion, wherein the patterned masking layer defines both a first and second bitcell; and forming the first and second bitcell using the patterned masking layer, wherein each of the first and second bitcell comprises a select gate made from the first layer and a control gate made from the second layer.
摘要翻译： 一种方法包括在半导体衬底上形成栅极材料的第一层; 在第一层上形成硬掩模层; 形成开口 在所述硬掩模层和所述开口内形成电荷存储层; 在所述电荷存储层上形成栅极材料的第二层; 去除所述第二层的一部分和所述电荷存储层的覆盖所述硬掩模层的部分，其中所述第二层的第二部分保留在所述开口内; 在所述硬掩模层上并在所述第二部分上形成图案化掩模层，其中所述图案化掩模层限定第一和第二位单元; 以及使用所述图案化掩模层形成所述第一和第二位单元，其中所述第一和第二位单元中的每一个包含由所述第一层制成的选择栅极和由所述第二层制成的控制栅极。
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公开(公告)号：US20090111229A1
公开(公告)日：2009-04-30
申请号：US11931376
申请日：2007-10-31
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/42348 , H01L29/66825 , H01L29/66833
摘要： A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate.
摘要翻译： 一种方法通过提供半导体衬底并形成覆盖选择栅极形成分离栅极存储单元。 选择栅极具有预定的高度并且与半导体衬底电绝缘。 随后形成电荷存储层，覆盖并邻近选择栅极。 随后通过电荷存储层形成与选择栅极相邻并分离的控制栅极。 电荷存储层也位于控制栅极和半导体衬底之间。 控制门最初具有高于选择门的预定高度的高度。 控制栅极凹入到小于选择栅极的预定高度的控制栅极高度。 源极和漏极形成在半导体衬底中。
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