公开(公告)号：US10261256B2

公开(公告)日：2019-04-16

申请号：US15546283

申请日：2015-01-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Raymond G Beausoleil ,  Marco Fiorentino ,  Jason Pelc ,  Charles M Santori ,  Terrel L Morris

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/26 ,  H04B10/80 ,  G02B6/122 ,  G02B6/14 ,  G02B6/28 ,  G02B6/00

Abstract: One example includes an apparatus that includes a plurality of input/output (I/O) ports and a body portion. The plurality of I/O ports can be arranged at a plurality of peripheral surfaces of the body portion. The body portion includes a solid dielectric material having a substantially constant index of refraction. The body portion also includes parallel planar surfaces spaced apart by and bounded by the plurality of peripheral surfaces. The solid dielectric material in the body portion can be writable via a laser-writing process to form an optical waveguide extending between a set of the plurality of I/O ports.

公开(公告)号：US20190089129A1

公开(公告)日：2019-03-21

申请号：US16132070

申请日：2018-09-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Di Liang ,  Geza Kurczveil ,  Raymond G. Beausoleil ,  Marco Fiorentino

IPC: H01S5/343 ,  H01S3/23 ,  H01S3/063 ,  H01S5/02 ,  H01S5/34 ,  H01S5/042 ,  H01S5/32 ,  H01S5/347 ,  H01S5/026 ,  H01S5/10

CPC classification number: H01S5/343 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/0216 ,  H01S5/0261 ,  H01S5/0424 ,  H01S5/1032 ,  H01S5/3211 ,  H01S5/3412 ,  H01S5/347

Abstract: An example method of manufacturing a semiconductor device. A first wafer may be provided that includes a first layer that contains quantum dots. A second wafer may be provided that includes a buried dielectric layer and a second layer on the buried dielectric layer. An interface layer may be formed on at least one of the first layer and the second layer, where the interface layer may be an insulator, a transparent electrical conductor, or a polymer. The first wafer may be bonded to the second wafer by way of the interface layer.

公开(公告)号：US20180081203A1

公开(公告)日：2018-03-22

申请号：US15272856

申请日：2016-09-22

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Tsung-Ching Huang ,  Chin-Hui Chen ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: G02F1/01 ,  H03K5/06 ,  G02F1/025

CPC classification number: G02F1/0121 ,  G02F1/025 ,  G02F1/3132 ,  H03K5/06 ,  H03K5/14 ,  H03K2005/00019 ,  H04B10/2507 ,  H04B10/69

Abstract: Examples described herein relate to a driver circuit. In an example, the circuit includes a first input for receiving a first signal and a second input for receiving a second signal that is an inverse of the first signal. The circuit also includes a first driver array electrically coupling the first input to a first DC isolator and a first delay tap line electrically coupling the second input to the first DC isolator. The circuit further includes a second driver array electrically coupling the second input to a second DC isolator and a second delay tap line electrically coupling the first input to the second DC isolator. A carrier controller of the circuit is electrically coupled between the first DC isolator and the second DC isolator.

公开(公告)号：US20240329489A1

公开(公告)日：2024-10-03

申请号：US18192509

申请日：2023-03-29

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Yiwei Peng ,  Wayne Sorin ,  Yuan Yuan ,  Stanley Cheung ,  Thomas Van Vaerenbergh ,  Marco Fiorentino

IPC: G02F1/21 ,  G02F1/225 ,  G06N3/04

CPC classification number: G02F1/212 ,  G02F1/225 ,  G06N3/04 ,  G02F2203/50

Abstract: An example Mach-Zehnder interferometer (MZI) is provided. The MZI includes a first waveguide arm and a second waveguide arm coupled to the first waveguide arm via a pair of optical couplers. In the proposed MZI, at least one of the first waveguide arm and the second waveguide arm includes a plurality of Bragg-grating segments and a phase-shifter segment formed between adjacent Bragg-grating segments of the plurality of Bragg-grating segments. The phase-shifter segment formed between adjacent Bragg-grating segments induces a predefined phase-shift in an optical signal propagating through respective at least one of the first waveguide arm and the second waveguide arm, resulting in increased linearity an optical transmission via the MZI.

公开(公告)号：US11681103B2

公开(公告)日：2023-06-20

申请号：US16883969

申请日：2020-05-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Peng Sun ,  Mir Ashkan Seyedi ,  Thomas Van Vaerenbergh ,  Marco Fiorentino

IPC: G02B6/293 ,  G02B6/136 ,  G02B6/12

CPC classification number: G02B6/29338 ,  G02B6/136 ,  G02B6/12

Abstract: Embodiments of the present disclosure provide etch-variation tolerant optical coupling components and processes for making the same. An etch-variation tolerant geometry is determined for at least one waveguide of an optical coupling component (e.g., a directional coupler). The geometry is optimized such that each fabricated instance of an optical component design with the etch-variation tolerant geometry has substantially the same coupling ratio at any etch depth between a shallow etch depth and a deep etch depth.

公开(公告)号：US11114409B2

公开(公告)日：2021-09-07

申请号：US16777569

申请日：2020-01-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Mir Ashkan Seyedi ,  Marco Fiorentino

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: Examples herein relate to optoelectronic assemblies. In particular, implementations herein relate to an optoelectronic assembly formed via a chip on wafer on substrate (CoWoS) process. The optoelectronic assembly includes a substrate, an interposer, and an electronic integrated circuit (EIC). Each of the substrate, interposer, and EIC includes opposing first and second sides. The EIC is flip-chip assembled to the first side of the interposer, and the interposer with the EIC assembled thereto is flip-chip assembled to the first side of the substrate. An overmold layer extends over the first side of the interposer and encapsulates the EIC. The overmold layer includes a cavity such that a region of the first side of the interposer is exposed. An optical component is positioned within the cavity and coupled to the first side of the interposer.

公开(公告)号：US10673535B2

公开(公告)日：2020-06-02

申请号：US16085364

申请日：2016-04-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Cheng Li ,  Kunzhi Yu ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04B10/69 ,  H04B10/516 ,  H04B10/63 ,  H04L25/49

Abstract: An example optical receiver may have an optical receiver front-end, four slicers, and a logic block. The optical receiver front-end may include a transimpedance amplifier to convert a photodiode output signal to a voltage signal. Three of the slicers may be data slicers, and one of the slicers may be an edge slicer. The slicers may each: shift the voltage signal based on an offset voltage set for the respective slicer, determine whether the shifted voltage signal is greater than a threshold value and generate a number of comparison signals based on the determining, and generate multiple digital signals by demuxing the comparison signals. The logic block may perform PAM-4 to binary decoding based on the data signals output by the data slicers and clock-and-data-recovery based on the digital signals output by the edge slicer.

公开(公告)号：US10658539B2

公开(公告)日：2020-05-19

申请号：US14988334

申请日：2016-01-05

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Zhen Peng ,  Nathaniel Quitoriano ,  Marco Fiorentino

IPC: H01L33/00 ,  G02B5/18 ,  G02B19/00 ,  H01L33/10 ,  H01L33/52 ,  H01L33/58 ,  H01L33/60

Abstract: A light emitting diode device is described which includes at least one planar non-periodic high-index-contrast grating. The light emitting diode device includes a cavity formed between a reflective optical element and a transmissive optical element. One or both of the optical elements can be a planar non-periodic high-index-contrast grating. The transmissive optical element can be a collimating lens used to collimate incident beams of light while the reflective optical element can be a parabolic reflector used to reflect incident beams of light along a direction opposite to an incidence direction. A light emitter can be disposed within the cavity and can emit beams of light.

公开(公告)号：US10651942B2

公开(公告)日：2020-05-12

申请号：US16275727

申请日：2019-02-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Cheng Li ,  Jim Huang ,  Ashkan Seyedi ,  Marco Fiorentino ,  Raymond G. Beausoleil

IPC: H04B10/00 ,  H04B10/50 ,  G02F1/225 ,  G02F1/01 ,  G02F1/21

Abstract: One example includes a bias-based Mach-Zehnder modulation (MZM) system. The system includes a Mach-Zehnder modulator to receive and split an optical input signal and to provide an intensity-modulated optical output signal based on a high-frequency data signal to modulate a relative phase of the split optical input signal to transmit data and based on a bias voltage to modulate the relative phase of the split optical input signal to tune the Mach-Zehnder modulator. The system also includes a bias feedback controller to compare a detection voltage associated with the intensity-modulated output signal with a reference voltage to measure an extinction ratio associated with an optical power of the intensity-modulated optical output signal and to adjust the bias voltage based on the comparison to substantially maximize the extinction ratio.

公开(公告)号：US10514508B2

公开(公告)日：2019-12-24

申请号：US15966362

申请日：2018-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kevin B. Leigh ,  Paul Kessler Rosenberg ,  Sagi Mathai ,  Mir Ashkan Seyedi ,  Michael Renne Ty Tan ,  Wayne Victor Sorin ,  Marco Fiorentino

IPC: G02B6/30

Abstract: In example implementations, an optical connector is provided. The optical connector includes a jumper holder, a base bracket, and an optical ferrule. The jumper holder holds a plurality of ribbon fibers. The base bracket is coupled to an electrical substrate to mate with the jumper holder. The optical ferrule is coupled to an end of each one of the plurality of ribbon fibers. The optical ferrule is laterally inserted into a corresponding orthogonal socket that is coupled to a silicon interposer on the electrical substrate to optically mate the optical ferrule to the orthogonal socket.