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58 条记录 (耗时 0.046 秒)

    Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell
    32.
    发明授权
    Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell 失效
    用于集成电路结构的碳纳米管存储单元，其具有可拆卸侧面间隔件，以允许访问存储器单元和用于形成这种存储器单元的

    公开(公告)号：US06955937B1

    公开(公告)日：2005-10-18

    申请号：US10917551

    申请日：2004-08-12

    申请人： Peter A. Burke ,  Sey-Shing Sun ,  Hong-Qiang Lu

    发明人： Peter A. Burke ,  Sey-Shing Sun ,  Hong-Qiang Lu

    IPC分类号： G11C13/02 ,  H01L21/00 ,  H01L27/10

    CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C13/025 ,  G11C2213/16 ,  Y10S977/943

    摘要： A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers. A silicon oxide layer is deposited over the structure and also anisotropically etched forming silicon oxide sidewall spacers on the polysilicon sidewall spacers. The polysilicon is wet etched with an etchant selective to adjacent materials to remove the polysilicon sidewalls spacers and all of the polysilicon in the chambers. Silicon oxide is formed over the structure and into the upper portion of the openings to seal the now empty chambers. A passivation layer may then be formed.

    摘要翻译： 一种用于集成电路的碳纳米管存储单元，其中室被构造成电介质材料如氮化硅的层，直到第一电接触。 这个房间里充满了多晶硅。 在氮化硅层和室之上形成一层碳纳米管垫或带。 在纳米管条之上形成电介质材料，例如氧化物层，并被图案化以形成一个向下到带状层的上部腔室，以使带状物移动到上部腔室或下部腔室中。 然后，上部室充满多晶硅。 在氧化物层上形成氮化硅层，并且向下形成接触开口，并且填充有钨，然后将其图案化以形成金属线。 任何暴露的氮化硅被去除。 在钨线上形成多晶硅层，并进行各向异性蚀刻以去除水平表面上的多晶硅，但留下多晶硅侧壁间隔物。 在结构上沉积氧化硅层，并且还各向异性地蚀刻在多晶硅侧壁间隔物上形成氧化硅侧壁间隔物。 用对相邻材料选择性的蚀刻剂湿式蚀刻多晶硅以去除多晶硅侧壁间隔物和室中的所有多晶硅。 在结构上形成氧化硅并进入开口的上部，以密封现在的空腔。 然后可以形成钝化层。

    TFEL device having multiple layer insulators
    33.
    发明授权
    TFEL device having multiple layer insulators 失效
    TFEL器件具有多层绝缘子

    公开(公告)号：US4897319A

    公开(公告)日：1990-01-30

    申请号：US221440

    申请日：1988-07-19

    申请人： Sey-Shing Sun

    发明人： Sey-Shing Sun

    IPC分类号： H05B33/12 ,  H05B33/22

    CPC分类号： H05B33/22 ,  H05B33/12 ,  Y10S428/917

    摘要： A structure for a thin-film electroluminescent (TFEL) device includes an EL phosphor layer sandwiched between a pair of insulator stacks, at least one of the stacks including a thin layer of silicon oxynitride in direct contact with the last grown side of the phosphor layer and a second thicker layer of barium tantalate. The silicon oxynitride layer has high resistivity, and when combined with a second insulator having a high dielectric constant, such as barium tantalate, produces an increase in luminance of the phosphor layer at conventional voltages. Both insulator stacks may include a silicon oxynitride layer, but this layer is in contact only with the last grown side of the EL phosphor layer. On the other side of the EL phosphor layer the high dielectric constant layer lies between the silicon oxynitride and the EL phosphor layer.

    摘要翻译： 用于薄膜电致发光（TFEL）器件的结构包括夹在一对绝缘体堆叠之间的EL荧光体层，至少一个堆叠包括与磷光体层的最后生长侧直接接触的氧氮化硅薄层 和第二厚的钡钽酸盐层。 氧氮化硅层具有高电阻率，并且当与具有高介电常数的第二绝缘体（例如钽酸钡）组合时，在常规电压下产生荧光体层的亮度增加。 两个绝缘体堆叠可以包括氧氮化硅层，但是该层仅与EL荧光体层的最后生长侧接触。 在EL荧光体层的另一侧，高介电常数层位于氮氧化硅和EL荧光体层之间。

    Self-aligned cell integration scheme
    36.
    发明授权
    Self-aligned cell integration scheme 失效
    自对准单元集成方案

    公开(公告)号：US07915122B2

    公开(公告)日：2011-03-29

    申请号：US11312849

    申请日：2005-12-20

    申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

    IPC分类号： H01L21/336

    CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

    摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

    摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

    Bi-axial texturing of high-K dielectric films to reduce leakage currents
    37.
    发明授权
    Bi-axial texturing of high-K dielectric films to reduce leakage currents 失效
    高K电介质膜的双轴纹理化以减少漏电流

    公开(公告)号：US07619272B2

    公开(公告)日：2009-11-17

    申请号：US11007392

    申请日：2004-12-07

    申请人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

    发明人： Wai Lo ,  Sey-Shing Sun ,  Wilbur Catabay

    IPC分类号： H01L29/76

    CPC分类号： H01L29/51 ,  C23C14/226 ,  C23C14/3442 ,  C23C14/46 ,  C23C16/486 ,  H01L21/02189 ,  H01L21/02266 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645

    摘要： The present invention is directed to a method of fabricating a high-K dielectric films having a high degree of crystallographic alignment at grain boundaries of the film. A disclosed method involves providing a substrate and then depositing a material used in forming the high-K dielectric film and also using an ion beam to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film. Another disclosed method involves providing a substrate and then angularly depositing a material onto the substrate in order to assist in the preferential formation of crystal lattices having a selected crystallographic orientation. The resultant dielectric film having a high degree of crystallographic alignment at grain boundaries of the film.

    摘要翻译： 本发明涉及制造在膜的晶界处具有高度晶体取向度的高K电介质膜的方法。 所公开的方法包括提供衬底，然后沉积用于形成高K电介质膜的材料，并且还使用离子束来辅助优选形成具有选定结晶取向的晶格。 所得的电介质膜在膜的晶界处具有高度的结晶取向度。 另一公开的方法包括提供衬底，然后将材料成角度地沉积到衬底上，以帮助优先形成具有选定结晶取向的晶格。 所得的电介质膜在膜的晶界处具有高度的结晶取向度。

    APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
    38.
    发明申请
    APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW 有权
    门盖边缘应用于更换门盖晶体管流程中的门长度CD

    公开(公告)号：US20080308882A1

    公开(公告)日：2008-12-18

    申请号：US12140773

    申请日：2008-06-17

    申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

    IPC分类号： H01L29/00

    CPC分类号： H01L29/49 ,  G02B6/3897 ,  G02B6/445 ,  H01L29/51 ,  H02G15/117

    摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

    摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

    Integrated barrier and seed layer for copper interconnect technology
    39.
    发明授权
    Integrated barrier and seed layer for copper interconnect technology 有权
    铜互连技术的集成屏障和种子层

    公开(公告)号：US07300869B2

    公开(公告)日：2007-11-27

    申请号：US10945777

    申请日：2004-09-20

    申请人： Sey-Shing Sun ,  Byung-Sung L. Kwak ,  Peter A. Burke

    发明人： Sey-Shing Sun ,  Byung-Sung L. Kwak ,  Peter A. Burke

    IPC分类号： H01L21/4763 ,  H01L29/45

    CPC分类号： H01L21/76844 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.

    摘要翻译： 集成的屏障和种子层，可用于在半导体器件中产生导电通路。 集成层的阻挡部分防止导电材料扩散到下面的电介质基底中，同时种子部分提供了沉积导电材料的适当基础。 集成层的阻挡部分由金属氮化物形成，而种子部分由钌或钌合金形成。 金属氮化物形成有效的阻挡层，而钌或钌合金形成金属如铜的有效晶种层。 在一些实施例中，集成层以使其组成从一个区域逐渐变化到下一个区域的方式形成。

    Method and structure for creating ultra low resistance damascene copper wiring
    40.
    发明授权
    Method and structure for creating ultra low resistance damascene copper wiring 有权
    制造超低电阻大马士革铜线的方法和结构

    公开(公告)号：US07196420B1

    公开(公告)日：2007-03-27

    申请号：US11259965

    申请日：2005-10-26

    申请人： Peter A. Burke ,  Hongqiang Lu ,  Sey-Shing Sun

    发明人： Peter A. Burke ,  Hongqiang Lu ,  Sey-Shing Sun

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76841

    摘要： A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.

    摘要翻译： 通过在通孔和沟槽结构的侧壁上形成诸如SiC或SiOC的薄介电膜来形成低电阻铜镶嵌互连结构，起到铜扩散阻挡层的作用。 通过各向异性蚀刻去除在沟槽结构的底部形成的电介质铜扩散屏障，以露出图案化的金属区域。 因此，残余电介质在结构的侧壁上形成电介质扩散阻挡膜，并与随后在沟槽中形成的金属扩散阻挡层耦合，形成铜扩散阻挡层，以保护大块电介质免受铜泄漏。