公开(公告)号：US06998343B1

公开(公告)日：2006-02-14

申请号：US10721971

申请日：2003-11-24

申请人： Grace Sun ,  Vladimir Zubkov ,  William K. Barth ,  Sethuraman Lakshminarayanan ,  Sey-Shing Sun ,  Agajan Suvkhanov ,  Hao Cui

发明人： Grace Sun ,  Vladimir Zubkov ,  William K. Barth ,  Sethuraman Lakshminarayanan ,  Sey-Shing Sun ,  Agajan Suvkhanov ,  Hao Cui

IPC分类号： H01L21/44

CPC分类号： H01L21/76867 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76841

摘要： A method for forming damascene interconnect copper diffusion barrier layers includes implanting calcium into the sidewalls of the trenches and vias. The calcium implantation into dielectric layers, such as oxides, is used to prevent Cu diffusion into oxide, such as during an annealing process step. The improved barrier layers of the present invention help prevent delamination of the Cu from the dielectric.

摘要翻译： 用于形成镶嵌互连铜扩散阻挡层的方法包括将钙植入沟槽和通孔的侧壁中。 诸如氧化物之类的介电层中的钙注入用于防止Cu扩散到氧化物中，例如在退火工艺步骤期间。 本发明的改进的阻挡层有助于防止Cu从电介质分层。

公开(公告)号：US07015096B1

公开(公告)日：2006-03-21

申请号：US10883137

申请日：2004-07-01

申请人： Vladimir Zubkov ,  Sey-Shing Sun

发明人： Vladimir Zubkov ,  Sey-Shing Sun

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L29/517

摘要： In one embodiment, bimetallic oxide compositions for gate dielectrics that include two or more of the elements Ca, Sr, Ba, Hf, and Zr are described.

摘要翻译： 在一个实施方案中，描述了包括元素Ca，Sr，Ba，Hf和Zr中的两种或更多种的栅极电介质的双金属氧化物组合物。

公开(公告)号：US09231204B2

公开(公告)日：2016-01-05

申请号：US13630795

申请日：2012-09-28

申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Eric R. Dickey ,  Michael Stephen Bowen ,  Sey-Shing Sun

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Eric R. Dickey ,  Michael Stephen Bowen ,  Sey-Shing Sun

IPC分类号： G11C11/00 ,  H01L45/00 ,  G11C13/00

CPC分类号： H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： Embodiments include low voltage embedded memory having conductive oxide and electrode stacks. A material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.

摘要翻译： 实施例包括具有导电氧化物和电极堆叠的低电压嵌入式存储器。 用于存储元件的材料层堆叠包括第一导电电极。 导电氧化物层设置在第一导电电极上。 导电氧化物层中具有多个氧空位。 第二电极设置在导电氧化物层上。

公开(公告)号：US20140092666A1

公开(公告)日：2014-04-03

申请号：US13630795

申请日：2012-09-28

申请人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Eric R. Dickey ,  Michael Stephen Bowen ,  Sey-Shing Sun

发明人： Elijah V. Karpov ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Eric R. Dickey ,  Michael Stephen Bowen ,  Sey-Shing Sun

IPC分类号： H01L45/00 ,  G11C11/00

CPC分类号： H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.

摘要翻译： 描述具有导电氧化物和电极堆叠的低电压嵌入式存储器。 例如，用于存储元件的材料层堆叠包括第一导电电极。 导电氧化物层设置在第一导电电极上。 导电氧化物层中具有多个氧空位。 第二电极设置在导电氧化物层上。

公开(公告)号：US07405116B2

公开(公告)日：2008-07-29

申请号：US10916322

申请日：2004-08-11

申请人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

发明人： Richard J. Carter ,  Wai Lo ,  Sey-Shing Sun ,  Hong Lin ,  Verne Hornback

IPC分类号： H01L21/338

CPC分类号： H01L29/6656 ,  H01L21/823828 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

摘要翻译： 保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。 衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。 该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于 模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

公开(公告)号：US07205673B1

公开(公告)日：2007-04-17

申请号：US11283044

申请日：2005-11-18

申请人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

发明人： Jayanthi Pallinti ,  Dilip Vijay ,  Hemanshu Bhatt ,  Sey-Shing Sun ,  Hong Ying ,  Chiyi Kao

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53219 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.

摘要翻译： 一种接合焊盘结构，其包括铝接合焊盘，其包括一个或多个掺杂剂，其有效地将IMC的生长控制到标称电平，尽管晶片中存在高拉伸应力。 例如，铝可以掺杂1-2原子％的Mg。 或者，可以使用Pd或Si，或者可以使用诸如Cu或Si的元素作为掺杂剂，以便降低晶片中的整体拉伸应力。 这可以控制IMC的异常生长，从而阻止IMC裂纹形成。 可以使用掺杂剂的组合来控制拉伸应力并且还稍微改变金 - 铝界面，从而实现均匀和薄的IMC形成。 这倾向于减少或消除否则在引线键合转移时会发生的任何空隙或裂纹。

公开(公告)号：US07064062B2

公开(公告)日：2006-06-20

申请号：US10738761

申请日：2003-12-16

申请人： Wai Lo ,  Verne Hornback ,  Wilbur G. Catabay ,  Wei-Jen Hsia ,  Sey-Shing Sun

发明人： Wai Lo ,  Verne Hornback ,  Wilbur G. Catabay ,  Wei-Jen Hsia ,  Sey-Shing Sun

IPC分类号： H01L21/4763 ,  B05D3/02

CPC分类号： H01L21/02142 ,  H01L21/02323 ,  H01L21/3115 ,  H01L21/31604 ,  H01L21/31612 ,  H01L21/31637 ,  H01L21/31645

摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

摘要翻译： 本发明提供了在半导体晶片上形成高k电介质层的方法。 金属硅酸盐介电层最初沉积在晶片上。 将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。 根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。 根据另一个实施方案，金属硅酸盐包含III族金属。

公开(公告)号：US20050224358A1

公开(公告)日：2005-10-13

申请号：US10814059

申请日：2004-03-30

申请人： Byung-Sung Kwak ,  Jayanthi Pallinti ,  Sey-Shing Sun ,  William Barth ,  Wilbur Catabay

发明人： Byung-Sung Kwak ,  Jayanthi Pallinti ,  Sey-Shing Sun ,  William Barth ,  Wilbur Catabay

IPC分类号： C25D3/02 ,  C25D5/02 ,  C25D5/18 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/321 ,  H01L21/768

CPC分类号： H01L21/7684 ,  C25D3/02 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/76877

摘要： A metal layer formed on a semiconductor wafer is planarized by applying sequentially a deplating step, a plating step, and a relaxation step in a removal cycle. A series of cycles are performed sequentially in one embodiment to comprise a pass. The removal cycle is repeated in sequence until the pass is completed. The respective deplating and plating rates are adjusted so that the ratios of deplating rates to plating rates progressively decrease from an initial pass to a final pass. Organic additives are added to the electrolytic plating solution to control the plating portion of the cycle in a topography dependant fashion.

摘要翻译： 通过在去除循环中依次应用脱铝步骤，电镀步骤和弛豫步骤来平坦化在半导体晶片上形成的金属层。 在一个实施例中，顺序执行一系列循环以包括通过。 删除循环按顺序重复，直到通过完成。 调整各自的脱镀和电镀速率，使得脱铝速率与电镀速率的比率从初始通过到最终通过逐渐降低。 将有机添加剂添加到电解电镀溶液中以以地形依赖的方式控制循环的电镀部分。

公开(公告)号：US5939825A

公开(公告)日：1999-08-17

申请号：US759293

申请日：1996-12-02

申请人： Sey-Shing Sun ,  Jim Kane ,  P. Niel Yocom

发明人： Sey-Shing Sun ,  Jim Kane ,  P. Niel Yocom

IPC分类号： C09K11/56 ,  C09K11/61 ,  C09K11/62 ,  C09K11/64 ,  C09K11/66 ,  C09K11/74 ,  C09K11/77 ,  H05B33/14 ,  H05B33/10

CPC分类号： H05B33/14 ,  C09K11/613 ,  C09K11/625 ,  C09K11/643 ,  C09K11/663 ,  C09K11/7421 ,  C09K11/7703

摘要： A light emitting phosphor having improved luminance is incorporated into an ACTFEL device having front and rear electrode sets, a pair of insulators sandwiched between the front and rear electrode sets, and a thin film electroluminescent laminar stack which includes a phosphor layer having the formula M.sup.II S:D,H,F where M.sup.II is taken from the group calcium, strontium, barium, and magnesium, S=sulfur, D is taken from the group copper, lead, gold, silver, magnesium, antimony, bismuth and arsenic, H is taken from the group fluorine, chlorine, bromine, and iodine, and F is taken from the group gallium, indium, aluminum, germanium, silicon, lanthanum, scandium, and yttrium. Deep blue and green chromaticity phosphors may be obtained through selection of multiple co-dopants and adjusting their relative concentrations.

公开(公告)号：US5677594A

公开(公告)日：1997-10-14

申请号：US509745

申请日：1995-08-01

申请人： Sey-Shing Sun ,  Michael S. Bowen

发明人： Sey-Shing Sun ,  Michael S. Bowen

IPC分类号： C09K11/88 ,  H05B33/14 ,  H05B33/00

CPC分类号： C09K11/886 ,  H05B33/14

摘要： An electroluminescent phosphor is sandwiched by a pair of insulating layers which are sandwiched by a pair of electrode layers to provide an AC TFEL device. The phosphor consists of a host material and an activator dopant that is preferably a rare earth. The host material is an alkaline earth sulfide, an alkaline earth selenide or an alkaline earth sulfide selenide that includes a Group 3A metal selected from aluminum, gallium and indium. The phosphor is preferably fabricated by first depositing a layer of the alkaline earth sulfide, alkaline earth selenide or alkaline earth sulfide selenide including the rare earth dopant therein, depositing thereon an overlayer selected from an alkaline earth thiogallate, an alkaline earth thioindate, an alkaline earth thioaluminate, an alkaline earth selenoaluminate, an alkaline earth selenoindate, or an alkaline earth selenogallate. The two layers are annealed at a temperature preferably between 750.degree. and 850.degree. C.

摘要翻译： 电致发光荧光体被一对绝缘层夹在一起，被一对电极层夹在中间以提供AC TFEL装置。 荧光体由主体材料和优选为稀土的活化剂掺杂剂组成。 主体材料是碱土金属硫化物，碱土金属硒化物或碱土金属硫化物硒化物，其包括选自铝，镓和铟的3A族金属。 优选通过首先在其中沉积包括稀土掺杂剂的碱土金属硫化物，碱土金属硒化物或碱土金属硫化物硒的层来沉积磷光体，其上沉积有选自碱土金属硫羟酸盐，碱土金属硫酸盐，碱土金属 硫酸铝酸盐，碱土硒硒铝酸盐，碱土硒酸盐或碱土金属硒酸盐。 两层在优选750〜850℃的温度下退火。