公开(公告)号：US06853022B2

公开(公告)日：2005-02-08

申请号：US10352987

申请日：2003-01-29

申请人： Tsuyoshi Koga ,  Yoshiyuki Ishigaki ,  Motoi Ashida ,  Yukio Maki ,  Yasuhiro Fujii ,  Tomohiro Hosokawa ,  Takashi Terada ,  Makoto Dei ,  Yasuichi Masuda

发明人： Tsuyoshi Koga ,  Yoshiyuki Ishigaki ,  Motoi Ashida ,  Yukio Maki ,  Yasuhiro Fujii ,  Tomohiro Hosokawa ,  Takashi Terada ,  Makoto Dei ,  Yasuichi Masuda

IPC分类号： H01L27/108 ,  G11C11/402 ,  G11C11/412 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/4023 ,  G11C11/412 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/11 ,  H01L27/1108

摘要： A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

摘要翻译： 一种半导体存储器件，其主要存储部分是存储电荷作为二进制信息的电容器，以及控制向电容器的电荷输入/输出的存取晶体管，并且不需要刷新。 半导体存储器件包括具有存储节点的电容器，该存储节点位于半导体衬底之上，并且保持对应于存储的二进制信息的逻辑电平的电荷，位于半导体衬底表面上的存取晶体管，并控制累积在该半导体衬底表面上的电荷的输入/输出 电容器和位于半导体衬底上的锁存电路，并保持电容器存储节点的电位。 构成锁存电路的电路元件中的至少一个位于存取晶体管的上方。

公开(公告)号：US06242297B1

公开(公告)日：2001-06-05

申请号：US09527585

申请日：2000-03-17

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： P+-type source/drain regions for load transistors and N+-type source/drain regions for driver transistors are connected by means of P+-type source/drain region outgoing lead and N+-type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

摘要翻译： 负载晶体管的P +型源极/漏极区域和驱动晶体管的N +型源极/漏极区域通过P +型源极/漏极区域引出引线和N +型源极/漏极区域引出线通过直接接触孔连接。 用于负载晶体管和接地引线的漏极区域引出线以三维重叠的方式形成，并且连接到一侧的存储器节点的驱动晶体管的漏极区域引出线和连接到负载晶体管的漏极区域引出线 到另一侧的存储器节点也以三维重叠的方式形成，由此构成存储器节点电荷累加器。

公开(公告)号：US6147387A

公开(公告)日：2000-11-14

申请号：US116889

申请日：1998-07-16

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/91

CPC分类号： H01L27/1112 ,  Y10S257/904

摘要： An SRAM is provided with a high-resistance element for loading including a high-resistance portion, which extends onto adjacent memory cell. An interlayer insulating film is formed between the high-resistance portions.

摘要翻译： SRAM具有用于加载的高电阻元件，包括延伸到相邻存储单元上的高电阻部分。 在高电阻部分之间形成层间绝缘膜。

公开(公告)号：US6097103A

公开(公告)日：2000-08-01

申请号：US81283

申请日：1998-05-20

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/11

CPC分类号： H01L27/11 ,  H01L27/1104

摘要： P.sup.+ -type source/drain regions for load transistors and N.sup.+ -type source/drain regions for driver transistors are connected by means of P.sup.+ -type source/drain region outgoing lead and N.sup.+ -type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

摘要翻译： 负载晶体管的P +型源极/漏极区域和驱动晶体管的N +型源极/漏极区域通过P +型源极/漏极区域引出引线和N +型源极/漏极区域引出线通过直接接触孔连接。 用于负载晶体管和接地引线的漏极区域引出线以三维重叠的方式形成，并且连接到一侧的存储器节点的驱动晶体管的漏极区域引出线和连接到负载晶体管的漏极区域引出线 到另一侧的存储器节点也以三维重叠的方式形成，由此构成存储器节点电荷累加器。

公开(公告)号：US5659193A

公开(公告)日：1997-08-19

申请号：US654970

申请日：1996-05-28

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/76

CPC分类号： H01L27/0623 ,  H01L21/8249

摘要： The present invention is provided in order to suppress a leak current at an emitter-base junction and to implement a high-speed operation of a bipolar transistor. An n.sup.+ buried layer is formed at a surface of a p.sup.- silicon substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffused layer are formed on n.sup.+ buried layer. A p.sup.+ external base region and a p.sup.- base region are formed at a surface of n.sup.- epitaxial growth layer so as to be adjacent to each other. A first interlayer insulating layer having an opening is formed on p.sup.- base region. A groove which is located under opening and extends under first interlayer insulating layer is formed at a surface of p.sup.- base region. An n.sup.+ emitter region is formed at a bottom surface of groove within p.sup.- base region. A sidewall insulating layer is formed so as to expose n.sup.+ emitter region and to cover a sidewall of opening and to come into contact with a bottom surface of first interlayer insulating layer.

摘要翻译： 提供本发明是为了抑制发射极 - 基极结处的漏电流并实现双极晶体管的高速操作。 在p硅衬底的表面上形成n +掩埋层。 n +外延生长层和n +扩散层形成在n +掩埋层上。 在n外延生长层的表面形成p +外部基极区域和p基极区域，以便彼此相邻。 在p基极区上形成具有开口的第一层间绝缘层。 在p基底区域的表面上形成有位于开口下方并在第一层间绝缘层下方延伸的槽。 n +发射极区域形成在p基极区域内的沟槽的底面。 形成侧壁绝缘层，以露出n +发射极区域并覆盖开口的侧壁并与第一层间绝缘层的底表面接触。

公开(公告)号：US5480816A

公开(公告)日：1996-01-02

申请号：US273915

申请日：1994-07-12

申请人： Kimiharu Uga ,  Hiroki Honda ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

发明人： Kimiharu Uga ,  Hiroki Honda ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L21/265 ,  H01L21/225 ,  H01L21/385

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/7322

摘要： On an epitaxial layer (4) serving as a collector layer are formed an emitter layer (10), an intrinsic base layer (9) surrounding the emitter layer (10) while permitting the surface of the emitter layer (10) to be exposed, external base layers (8) and link base layers (7) lying between the intrinsic base layer (9) and external base layers (8). The intrinsic base layer between the emitter layer and the epitaxial layer serving as the collector layer has a relatively high impurity concentration, so that a collector-emitter breakdown voltage is not decreased. The link base layers between the intrinsic base layer and external base layers has a relatively low impurity concentration to suppress decrease in emitter-base junction breakdown voltage.

摘要翻译： 在用作集电极层的外延层（4）上形成发射极层（10），包围发射极层（10）的本征基极层（9），同时允许发射极层（10）的表面露出， 位于本征基底层（9）和外部基底层（8）之间的外部基底层（8）和连接基底层（7）。 用作集电极层的发射极层和外延层之间的本征基极层具有较高的杂质浓度，使得集电极 - 发射极击穿电压不降低。 本征基极层和外部基极层之间的基极层具有相对低的杂质浓度，以抑制发射极 - 基极结击穿电压的降低。

公开(公告)号：US20060267012A1

公开(公告)日：2006-11-30

申请号：US11498800

申请日：2006-08-04

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L31/00

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

公开(公告)号：US06831852B2

公开(公告)日：2004-12-14

申请号：US10442439

申请日：2003-05-22

申请人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

发明人： Yoshiyuki Ishigaki ,  Tsuyoshi Koga ,  Yasuhiro Fujii

IPC分类号： G11C1124

CPC分类号： G11C11/412 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.

摘要翻译： 半导体器件包括：电容器：具有杂质区域的存取晶体管，控制存储在电容器中的电荷的输入/输出，其中一个杂质区域电连接到电容器; 位于硅衬底上方的锁存电路，并存储电容器的存储节点的电位; 以及连接到存取晶体管T6的另一个杂质区的位线。 锁存电路的至少一部分形成在位线上方。

公开(公告)号：US06632716B2

公开(公告)日：2003-10-14

申请号：US09777453

申请日：2001-02-08

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： H01L21336

CPC分类号： H01L23/544 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5258 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region. In this semiconductor device, a distance defined from an outer edge of the gate electrode on the side of the first impurity region to another outer edge of the first insulating film on the side apart from the gate electrode is longer than a distance defined from an outer edge of the gate electrode on the side of the second impurity region to another outer edge of the second insulating film on the side apart from the gate electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底的一个主表面上的元件隔离膜; 元件形成区域，形成在主表面上并被元件隔离膜包围; 通过元件形成区上的栅极绝缘膜形成并在元件隔离膜上延伸的栅电极; 形成在元件形成区域中的第一和第二杂质区域从半导体衬底的表面露出的部分与元件隔离膜接触并且在栅电极下方彼此相对定位; 第一绝缘膜，形成在第一杂质区域上的栅电极附近，并且在元件隔离膜内延伸到栅极上并靠近栅电极的延伸部分; 以及形成在第二杂质区域上的栅电极附近的第二绝缘膜。 在该半导体器件中，从第一杂质区域侧的栅电极的外边缘到与栅电极相离的一侧的第一绝缘膜的另一外缘限定的距离比从外部限定的距离长 边缘在第二杂质区域侧的第二绝缘膜的另一个外边缘上的栅电极的边缘。

公开(公告)号：US06268627B1

公开(公告)日：2001-07-31

申请号：US09198611

申请日：1998-11-24

申请人： Yoshiyuki Ishigaki ,  Yasuhiro Fujii

发明人： Yoshiyuki Ishigaki ,  Yasuhiro Fujii

IPC分类号： H01L2976

CPC分类号： H01L27/1108

摘要： In an access transistor formed on a silicon substrate, its drain region is formed of n− type and n+ type drain regions and its source region is formed of n− type and n+ type source regions. In a driver transistor, its source region is formed of n− type and n++ type source regions and its drain regions is formed of n− type and n+ type drain regions. The n+ +type source region is formed deeper than the n+ type drain region. Accordingly, a semiconductor device ensuring improvement in a static noise margin while suppressing increase in manufacturing cost is provided.

摘要翻译： 在形成在硅衬底上的存取晶体管中，其漏极区由n型和n +型漏极区形成，其源区由n型和n +型源极区形成。 在驱动晶体管中，其源区由n型和n ++型源极区形成，其漏极区由n型和n +型漏极区形成。 n +型源极区域形成得比n +型漏极区域更深。 因此，提供了一种在抑制制造成本增加的同时确保静态噪声容限的改善的半导体装置。