公开(公告)号：US08582383B2

公开(公告)日：2013-11-12

申请号：US13070034

申请日：2011-03-23

申请人： Hiroyuki Takahashi

发明人： Hiroyuki Takahashi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4062

摘要： A semiconductor memory device includes a memory cell array having plural memory cells that require a refresh operation when retaining data; a read/write control unit that performs read-access or write-access of memory cell address specified for the memory cell array based on instructions from the outside; a refresh control unit that performs hidden-refresh of memory cells without control from the outside; and a schedule control unit that makes the refresh control unit perform hidden-refresh after the read/write control unit read-accesses the memory cell array, and that also makes the refresh control unit perform hidden-refresh before the read/write access control unit performs write-access.

摘要翻译： 半导体存储器件包括具有多个存储单元的存储单元阵列，当存储数据时需要刷新操作; 读/写控制单元，其基于来自外部的指令执行对存储单元阵列指定的存储单元地址的读取或写入; 刷新控制单元，其不从外部进行控制地进行存储单元的隐藏刷新; 以及调度控制单元，其使刷新控制单元在读/写控制单元读取存储单元阵列之后执行隐藏刷新，并且还使刷新控制单元在读/写访问控制单元之前进行隐藏刷新 执行写入访问。

公开(公告)号：US08553483B2

公开(公告)日：2013-10-08

申请号：US13602878

申请日：2012-09-04

申请人： Hiroyuki Takahashi ,  Masahiro Yoshida

发明人： Hiroyuki Takahashi ,  Masahiro Yoshida

IPC分类号： G11C7/00 ,  G11C7/02 ,  G11C7/10

CPC分类号： G11C7/1048 ,  G11C7/12 ,  G11C7/227 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A semiconductor memory device has: memory blocks; and a local bus connected to the memory blocks. Each memory block has: switches respectively provided between bit line pairs and the local bus and each of which is turned ON in response to a selection signal; a dummy local bus; first and second control circuits. The local bus and the dummy local bus are precharged to a first potential before a read operation. In the read operation, the first control circuit outputs the selection signal to a selected switch to electrically connect a selected bit line pair and the local bus, while the second control circuit supplies a second potential lower than the first potential to the dummy local bus. The first control circuit stops outputting the selection signal when a potential of the dummy local bus is decreased to a predetermined set potential that is between the first and second potentials.

摘要翻译： 半导体存储器件具有：存储器块; 以及连接到存储器块的本地总线。 每个存储块具有分别设置在位线对和本地总线之间的开关，并且每个开关响应于选择信号而导通; 虚拟当地巴士 第一和第二控制电路。 在读操作之前，本地总线和虚拟本地总线被预先充电到第一个电位。 在读取操作中，第一控制电路将选择信号输出到所选择的开关，以电连接所选位线对和局部总线，而第二控制电路将低于第一电位的第二电位提供给虚拟本地总线。 当虚拟局部总线的电位降低到第一和第二电位之间的预定设定电位时，第一控制电路停止输出选择信号。

公开(公告)号：US20130178071A1

公开(公告)日：2013-07-11

申请号：US13824028

申请日：2011-10-06

申请人： Hiroyuki Takahashi ,  Kazuhiko Yoshida

发明人： Hiroyuki Takahashi ,  Kazuhiko Yoshida

IPC分类号： H01L21/316

CPC分类号： H01L21/31662 ,  H01L21/02238 ,  H01L21/02255

摘要： Disclosed is a method of forming a thermal oxide film on a silicon single crystal wafer, which includes throwing the silicon single wafer into a heat treatment furnace; elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1; subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafter elevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1. Thus, there is provided a thermal oxide film formation method to suppress occurrence of slip dislocation and/or crack of the silicon single wafer during formation of the thermal oxide film.

摘要翻译： 公开了在硅单晶晶片上形成热氧化膜的方法，其包括将硅单晶片投掷到热处理炉中; 将热处理炉的升温至达到形成热氧化膜的温度T1，形成厚度为d1的热氧化膜; 随后将热处理炉的温度降低到低于温度T1的温度; 然后将热处理炉的温度升高到高于温度T1的温度T2，以另外形成厚度d2厚于厚度d1的热氧化膜。 因此，提供了一种热氧化膜形成方法，以在形成热氧化膜期间抑制硅单晶片的滑移位错和/或裂纹的发生。

公开(公告)号：US08482999B2

公开(公告)日：2013-07-09

申请号：US13600412

申请日：2012-08-31

申请人： Hiroyuki Takahashi ,  Tetsuo Fukushi

发明人： Hiroyuki Takahashi ,  Tetsuo Fukushi

IPC分类号： G11C7/12

CPC分类号： G11C11/4085 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

摘要翻译： 提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。 外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。 半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管， 并且响应于激活信号将一对位线预充电到预定电压。 预充电电路的激活信号是比第一电压高的第二电压。

公开(公告)号：US20130065682A1

公开(公告)日：2013-03-14

申请号：US13315433

申请日：2011-12-09

申请人： Toshiharu Izuno ,  Yuya Satoh ,  Hiroyuki Takahashi ,  Shugo Takahashi

发明人： Toshiharu Izuno ,  Yuya Satoh ,  Hiroyuki Takahashi ,  Shugo Takahashi

IPC分类号： A63F13/00 ,  A63F9/24

CPC分类号： A63F13/428 ,  A63F13/211 ,  A63F13/5252 ,  A63F13/5258 ,  A63F13/92 ,  A63F2300/105 ,  A63F2300/204 ,  A63F2300/6045 ,  A63F2300/6669 ,  A63F2300/6684 ,  A63F2300/8011 ,  A63F2300/8076

摘要： An exemplary embodiment provides a game system. The game system includes an operation apparatus and an information processing unit. The information processing unit includes a viewpoint mode switching unit for setting a first viewpoint mode for displaying on the display portion a display image picked up based on a position and a direction of image pick-up of a first virtual camera in a virtual space on a game when position data of the operation apparatus obtained by the sensor portion is in a first range and setting a second viewpoint mode for displaying on the display portion a display image picked up based on a position and a direction of image pick-up of a second virtual camera when the position data is in a second range, and a game processing unit for performing game processing in accordance with the operation input accepted by the operation portion.

摘要翻译： 示例性实施例提供了一种游戏系统。 游戏系统包括操作装置和信息处理单元。 信息处理单元包括：视点模式切换单元，用于设置第一视点模式，用于在显示部分上显示基于虚拟空间中的第一虚拟相机的位置和图像拾取方向拾取的显示图像 由所述传感器部获得的所述操作装置的位置数据处于第一范围，并且设定第二视点模式，用于在所述显示部分上显示基于第二图像拾取的位置和方向拾取的显示图像 当位置数据处于第二范围时的虚拟相机;以及游戏处理单元，用于根据操作部分所接受的操作输入进行游戏处理。

公开(公告)号：US08348734B2

公开(公告)日：2013-01-08

申请号：US11118331

申请日：2005-05-02

申请人： Hiroyuki Takahashi ,  Shugo Takahashi ,  Haruki Kodera ,  Yusuke Sugimoto ,  Toru Takamatsu ,  Toshiharu Izuno

发明人： Hiroyuki Takahashi ,  Shugo Takahashi ,  Haruki Kodera ,  Yusuke Sugimoto ,  Toru Takamatsu ,  Toshiharu Izuno

IPC分类号： A63F13/12

CPC分类号： A63F13/577 ,  A63F13/10 ,  A63F13/46 ,  A63F13/537 ,  A63F13/812 ,  A63F2300/303 ,  A63F2300/65 ,  A63F2300/8011

摘要： A game system moves a player character in a virtual game space in accordance with an operation by a player. Further, the player character's moving amount per predetermined unit time is detected at each predetermined time interval. A predetermined parameter (gage amount) value is calculated at each predetermined time interval based on the moving amount detected at each predetermined time interval. Also, the game system adds the predetermined parameter value calculated at each predetermined time interval for accumulation. In response to a predetermined operation performed by the player, the game system causes the player character to perform a predetermined motion (e.g., special shot) on a condition such that a value obtained as a result of the addition reaches a predetermined value.

摘要翻译： 游戏系统根据玩家的操作移动虚拟游戏空间中的玩家角色。 此外，在每个预定时间间隔检测每个预定单位时间的玩家角色的移动量。 基于在每个预定时间间隔检测到的移动量，在每个预定时间间隔计算预定参数（量具量）值。 此外，游戏系统添加在每个预定时间间隔计算的用于累积的预定参数值。 响应于玩家执行的预定操作，游戏系统使得玩家角色在使得作为添加的结果获得的值达到预定值的条件下执行预定的运动（例如，特殊镜头）。

公开(公告)号：US08330414B2

公开(公告)日：2012-12-11

申请号：US12513145

申请日：2006-11-08

申请人： Hiroyuki Takahashi ,  Hiroyuki Oku ,  Masanori Oshimi

发明人： Hiroyuki Takahashi ,  Hiroyuki Oku ,  Masanori Oshimi

IPC分类号： H02J7/00

CPC分类号： H02J50/10 ,  H01M10/44 ,  H01M10/446 ,  H01M10/448 ,  H02J7/025 ,  H02J50/60 ,  H02J50/80

摘要： A contactless charging system is made up of an electronic device and a contactless charger 200 that recharges the electronic device in a contactless manner. The electronic device transmits a full charge command indicating completion of charge. Upon receipt of the full charge command, the contactless charger shifts to a charge stop state in which charge of the electronic device is not performed. In the charge stop state, the contactless charger generates a load check signal for checking whether or not the electronic device is placed in the contactless charger in a rechargeable state, and transmits the signal. Further, the contactless charger also generates a charge restart check command for checking whether or not the electronic device requests recharge in a charge stop state, and transmits the command.

摘要翻译： 无接触充电系统由电子设备和非接触式充电器200组成，该电子设备以非接触方式对电子设备进行充电。 电子设备发送指示完成充电的完全充电命令。 在接收到完全充电命令时，非接触式充电器转移到不执行电子装置的充电的充电停止状态。 在充电停止状态下，非接触充电器产生负载检查信号，用于检查电子设备是否以可充电状态放置在非接触式充电器中，并发送信号。 此外，非接触充电器还产生用于检查电子设备是否在充电停止状态下请求充电的充电重启检查命令，并发送命令。

公开(公告)号：US08289534B2

公开(公告)日：2012-10-16

申请号：US11623951

申请日：2007-01-17

申请人： Hiroyuki Takahashi ,  Kazuhiko Ushiyama

发明人： Hiroyuki Takahashi ,  Kazuhiko Ushiyama

IPC分类号： G06K15/00

CPC分类号： B42B4/00 ,  B42C9/0031 ,  H04N1/00204 ,  H04N1/00244 ,  H04N1/00567 ,  H04N1/00639 ,  H04N1/00641 ,  H04N1/00649 ,  H04N1/00657 ,  H04N2201/0039

摘要： In a print system constituted so as to enable a supplying of sheets from a printing apparatus to a sheet processing apparatus, wherein the printing apparatus having a print unit that executes a print process of data of a job stored in a storage unit can store data of a plurality of jobs, wherein the sheet processing apparatus having a sheet processing unit that executes a sheet processing operation to sheets of job printed by the printing apparatus, a controller unit allows the print unit to execute a print process of a second job required before a sheet process of the second job in case that a plurality of jobs including the second job after a first job are accepted and in case that a sheet process of the first job required after a print process of the first job is in execution by the sheet processing unit.

摘要翻译： 在构成为能够从打印装置向纸张处理装置供应纸张的打印系统中，其中具有执行存储在存储单元中的作业的数据的打印处理的打印单元的打印装置可以存储 多个作业，其中，所述片材处理装置具有对由所述打印装置打印的作业片材执行片材处理操作的片材处理单元，所述打印单元允许所述打印单元执行在 在接受第一作业之后包括第二作业的多个作业的情况下以及在第一作业的打印处理之后所需的第一作业的纸张处理通过纸张处理执行的情况下的第二作业的纸张处理 单元。

公开(公告)号：US20120259525A1

公开(公告)日：2012-10-11

申请号：US13395034

申请日：2011-04-06

申请人： Hiroyuki Takahashi

发明人： Hiroyuki Takahashi

IPC分类号： B60T8/17 ,  B60T7/12

CPC分类号： B60T7/22 ,  B60T2201/022 ,  B60W10/06 ,  B60W10/18 ,  B60W30/09 ,  B60W2550/30 ,  B60W2550/302 ,  B60W2550/306 ,  B60W2550/308

摘要： A PCS ECU 20 in a PCS system 10 calculates TTC which is a brake operation timing of a host vehicle, on the basis of the relative velocity Vr between the host vehicle and an object, a predetermined deceleration amount ΔV caused by a brake operation of the host vehicle, and a deceleration a caused by the brake operation of the host vehicle. Thereby, the deceleration amount ΔV caused by the brake operation of the host vehicle is to be a set constant amount regardless of the relative velocity Vr between the host vehicle and the object. Accordingly, it is possible to ensure the deceleration amount ΔV caused by a more appropriate brake operation.

摘要翻译： PCS系统10中的PCS ECU 20基于本车辆和物体之间的相对速度Vr，由制动操作引起的预定减速度＆Dgr; V来计算作为本车辆的制动操作定时的TTC 并且由本车辆的制动操作引起的减速度a。 因此，无论本车辆和物体之间的相对速度Vr如何，由本车辆的制动操作引起的减速量＆Dgr; V成为设定的恒定量。 因此，可以确保由更适当的制动操作引起的减速量＆Dgr; V。

公开(公告)号：US08279691B2

公开(公告)日：2012-10-02

申请号：US12769141

申请日：2010-04-28

申请人： Hiroyuki Takahashi ,  Tetsuo Fukushi

发明人： Hiroyuki Takahashi ,  Tetsuo Fukushi

IPC分类号： G11C7/12

CPC分类号： G11C11/4085 ,  G11C7/062 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： Provided is a semiconductor integrated device including a semiconductor memory circuit and a peripheral circuit of the semiconductor memory circuit. The peripheral circuit includes a first transistor having a first voltage as a breakdown voltage of a gate oxide film. The semiconductor memory circuit includes a pair of bit lines, one of the pair of bit lines being connected to a gate transistor of a memory cell, and a precharge circuit that includes a transistor having a breakdown voltage substantially equal to that of the first transistor, and precharges the pair of bit lines to a predetermined voltage in response to an activation signal. The activation signal of the precharge circuit is a second voltage higher than the first voltage.

摘要翻译： 提供一种包括半导体存储电路和半导体存储电路的外围电路的半导体集成器件。 外围电路包括具有作为栅氧化膜的击穿电压的第一电压的第一晶体管。 半导体存储器电路包括一对位线，一对位线中的一个连接到存储单元的栅极晶体管，以及预充电电路，其包括具有基本上等于第一晶体管的击穿电压的晶体管， 并且响应于激活信号将一对位线预充电到预定电压。 预充电电路的激活信号是比第一电压高的第二电压。