公开(公告)号：US20240266349A1

公开(公告)日：2024-08-08

申请号：US18433779

申请日：2024-02-06

Applicant: IMEC VZW

Inventor： Gioele Mirabelli ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/06 ,  H10B10/00

CPC classification number: H01L27/092 ,  H01L23/5286 ,  H01L27/0688 ,  H10B10/12

Abstract: This disclosure relates to complementary field effect transistor (CFET) devices, and provides improved routability of the transistor structures in a CFET cell. The disclosure presents a CFET cell that includes a first transistor structure in a first tier and a second transistor structure in a second tier above the first tier. A first power rail is arranged below the first tier and connected to the first transistor structure from below, and a second power rail is formed in a first metal layer and connected to the second transistor structure from a first side. A set of signal routing lines formed in a second metal layer above the second tier is connected to the first and second transistor structure from above. Further, a signal routing structure formed in a metal zero (M0) layer is connected to the first transistor structure and/or to the second transistor structure from a second side.

公开(公告)号：US20230206996A1

公开(公告)日：2023-06-29

申请号：US18068330

申请日：2022-12-19

Applicant: IMEC VZW

Inventor： Shairfe Muhammad Salahuddin ,  Julien Ryckaert

IPC: G11C11/419 ,  H01L23/522 ,  H01L23/528 ,  H10B80/00 ,  H10B10/00 ,  H01L25/16

CPC classification number: G11C11/419 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/16 ,  H10B10/12 ,  H10B80/00

Abstract: A multiport memory cell for register files is disclosed. Vertically stacked top and bottom tier of the memory cell are electrically interconnected through a pair of vias and comprise each an active device layer and a metal layer stack. The memory cell is partitioned to have a latching circuit and at least one write port located in the bottom tier and at least two read ports in the top tier. A word line trace for controlling the at least one write port is formed in the bottom tier metal layer stack and comprises two terminal sections and one intermediate section oriented perpendicularly to the terminal sections. The intermediate section is arranged between the pair of vias in a height direction of the memory cell.

公开(公告)号：US20230178640A1

公开(公告)日：2023-06-08

申请号：US18060954

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi

IPC: H01L29/775 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439

Abstract: A FET device (100) is provided, the FET device including a substrate (102), a source body (120), a drain body (130) and a set of vertically spaced apart channel layers (150) extending between the source and drain body in a first direction along the substrate (102), the source body (120) comprising a common source body portion (122) arranged at a first lateral side of the set of channel layers (150) and a set of vertically spaced apart source prongs (124) protruding from the common source body portion (122) in a second direction along the substrate (102), transverse to the first direction, the drain body (130) comprising a common source body portion (132) arranged at the first lateral side of the set of channel layers (150) and a set of drain prongs (134) protruding from the common drain body portion (132) in the second direction; and a gate body (140) comprising a common gate body portion (142) arranged at a second lateral side of the channel layer (150), opposite the first lateral side, and a set of gate prongs (144) protruding from the common gate body gate portion (142) in a third direction along the substrate (102), opposite the first direction; wherein each channel layer (150) comprises a first side (150aa, 150ba) and an opposite second side (150ab, 150bb), the first side arranged in abutment with a topside or an underside of a pair of source and drain prongs (124a, 134a) and the second side (150ab, 150bb) facing a gate prong (144a, 144b).

公开(公告)号：US20230178635A1

公开(公告)日：2023-06-08

申请号：US18074294

申请日：2022-12-02

Applicant: IMEC VZW

Inventor： Aryan Afzalian ,  Julien Ryckaert ,  Naoto Horiguchi ,  Boon Teik Chan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/308 ,  H01L21/322 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L29/785 ,  H01L29/0847 ,  H01L29/1033 ,  H01L21/308 ,  H01L21/322 ,  H01L21/0262

Abstract: A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.

公开(公告)号：US11381242B2

公开(公告)日：2022-07-05

申请号：US17063003

申请日：2020-10-05

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.

公开(公告)号：US11342261B2

公开(公告)日：2022-05-24

申请号：US16721277

申请日：2019-12-19

Applicant: IMEC VZW

Inventor： Stefan Cosemans ,  Julien Ryckaert ,  Zsolt Tokei

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend.

公开(公告)号：US11335597B2

公开(公告)日：2022-05-17

申请号：US16945858

申请日：2020-08-01

Applicant: IMEC VZW

Inventor： Eugenio Dentoni Litta ,  Anshul Gupta ,  Julien Ryckaert ,  Boon Teik Chan

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8234

Abstract: A method for forming a buried metal line in a substrate includes forming, at a position between a pair of semiconductor structures protruding from the substrate, a metal line trench in the substrate at a level below a base of each semiconductor structure of the pair. Forming the metal line trench includes etching an upper trench portion in the substrate, forming a spacer on sidewall surfaces of the upper trench portion that expose a bottom surface of the upper trench portion, and, while the spacer masks the sidewall surfaces, etching a lower trench portion by etching the substrate via the upper trench portion such that a width of the lower trench portion exceeds a width of the upper trench portion. The method further includes forming the metal line in the metal line trench.

公开(公告)号：US20210183711A1

公开(公告)日：2021-06-17

申请号：US17110604

申请日：2020-12-03

Applicant: IMEC vzw

Inventor： Eugenio Dentoni Litta ,  Juergen Boemmels ,  Julien Ryckaert ,  Naoto Horiguchi ,  Pieter Weckx

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66

Abstract: In one aspect, a method of forming a semiconductor device, can comprise forming a first transistor structure and a second transistor structure separated by a trench. The first and the second transistor structures can comprise a plurality of stacked nanosheets forming a channel structure, and a source portion and a drain portion horizontally separated by the channel structure. A first and a second spacer can beformed in the trench at sidewalls of the transistor structures, both protruding above a top surface of the transistor structures. The method can comprise applying a first mask layer including an opening exposing the first spacer at a first source/drain portion of the first transistor structure and covering the second spacer, partially etching the exposed first spacer through the opening, exposing at least parts of a sidewall of the first source/drain portion of the first transistor structure, and removing the mask layer. The method can further comprise depositing a contact material over the transistor structures and the first and second spacer, filling the trench and contacting the first source/drain portion of the first transistor structure, and etching back the contact material layer below a top surface of the second spacer.

公开(公告)号：US11018235B2

公开(公告)日：2021-05-25

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L27/11 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/06 ,  H01L29/417

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US20200083234A1

公开(公告)日：2020-03-12

申请号：US16565112

申请日：2019-09-09

Applicant: IMEC vzw

Inventor： Shairfe Muhammad Salahuddin ,  Jan Van Houdt ,  Julien Ryckaert ,  Alessio Spessot

IPC: H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  G11C11/22 ,  H01L27/11587 ,  H01L27/11592

Abstract: The disclosed technology is generally directed to semiconductor integrated circuit devices and more particularly to a three-transistor random access memory (3T RAM) device, and a method of fabricating and operating the same. In one aspect, a 3T RAM cell includes a ferroelectric-based field effect transistor (FeFET) having a first gate connected as a storage node and a second transistor connected between the FeFET and a read bit line having a second gate connected to a read word line. The 3T RAM cell also includes a third transistor connected between the storage node and a write bit line having a third gate connected to a write word line.