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    SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS
    31.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING HORIZONTAL TILE OPERATIONS 审中-公开

    公开(公告)号：US20190042261A1

    公开(公告)日：2019-02-07

    申请号：US16131382

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Christopher J. HUGHES ,  Bret TOLL ,  Dan BAUM ,  Elmoustapha OULD-AHMED-VALL ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Disclosed embodiments relate to systems and methods for performing instructions specifying horizontal tile operations. In one example, a processor includes fetch circuitry to fetch an instruction specifying a horizontal tile operation, a location of a M by N source matrix comprising K groups of elements, and locations of K destinations, wherein each of the K groups of elements comprises the same number of elements, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction by generating K results, each result being generated by performing the specified horizontal tile operation across every element of a corresponding group of the K groups, and writing each generated result to a corresponding location of the K specified destination locations.

    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER
    32.
    发明申请
    APPARATUS AND METHOD TO REVERSE AND PERMUTE BITS IN A MASK REGISTER 审中-公开

    公开(公告)号：US20180039497A1

    公开(公告)日：2018-02-08

    申请号：US15785016

    申请日：2017-10-16

    Applicant: Intel Corporation

    Inventor： Elmoustapha OULD-AHMED-VALL ,  Robert VALENTINE

    IPC: G06F9/30

    CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098

    Abstract: An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

    Machine Level Instructions to Compute a 3D Z-Curve Index from 3D Coordinates
    33.
    发明申请
    Machine Level Instructions to Compute a 3D Z-Curve Index from 3D Coordinates 审中-公开
    从3D坐标计算3D Z曲线索引的机器级别说明

    公开(公告)号：US20160139919A1

    公开(公告)日：2016-05-19

    申请号：US14542499

    申请日：2014-11-14

    Applicant: Intel Corporation

    Inventor： Arnold Kerry EVANS ,  Elmoustapha OULD-AHMED-VALL

    IPC: G06F9/30 ,  G06F9/355 ,  G06F9/38

    CPC classification number: G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/355 ,  G06F9/3802 ,  G06F9/3895

    Abstract: In one embodiment, a processor includes 32-bit and 64-bit machine level instructions to compute a 3D Z-curve Index. A processor decode unit is configured to decode a z-curve ordering instruction having three source operands, each operand associated with one of a first, second, or third coordinate and a processor execution unit is configured to execute the decoded instruction before outputting the 3D Z-curve index to a location specified by a destination operand.

    Abstract translation: 在一个实施例中，处理器包括用于计算3D Z曲线索引的32位和64位机器级指令。 处理器解码单元被配置为解码具有三个源操作数的z曲线排序指令，每个操作数与第一，第二或第三坐标之一相关联，并且处理器执行单元被配置为在输出3D Z之前执行解码指令 -curve索引到目标操作数指定的位置。

    EFFICIENT DIVIDE AND ACCUMULATE INSTRUCTION WHEN AN OPERAND IS EQUAL TO OR NEAR A POWER OF TWO
    39.
    发明申请
    EFFICIENT DIVIDE AND ACCUMULATE INSTRUCTION WHEN AN OPERAND IS EQUAL TO OR NEAR A POWER OF TWO 有权

    公开(公告)号：US20220197634A1

    公开(公告)日：2022-06-23

    申请号：US17129693

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Elmoustapha OULD-AHMED-VALL

    IPC: G06F9/30

    Abstract: Techniques and apparatuses for performing a near multiply and accumulate instruction are described. An apparatus includes decoder circuitry to decode an instruction, the instruction to include a field for an identifier of a first source operand, a field for an identifier of a second source operand, and a field for an identifier of a third source operand. The apparatus also includes execution circuitry to execute the decoded instruction to perform a division on a pair of data elements from the first and second source operands to produce a quotient data element via a shift operation when at least one data element in the pair of data elements is equal to a power of two or near a power of two or via a division operation on the pair of data elements when the pair of data elements is neither equal to a power of two or near a power of two.

    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS
    40.
    发明申请
    SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILES AS 1D VECTORS 有权

    公开(公告)号：US20210318874A1

    公开(公告)日：2021-10-14

    申请号：US17240882

    申请日：2021-04-26

    Applicant: INTEL CORPORATION

    Inventor： Bret TOLL ,  Christopher J. HUGHES ,  Dan BAUM ,  Elmoustapha OULD-AHMED-VALL ,  Raanan SADE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Alexander F. HEINECKE

    IPC: G06F9/30

    Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

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