公开(公告)号：US10892335B2

公开(公告)日：2021-01-12

申请号：US16341010

申请日：2016-12-01

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Gilbert W. Dewey ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

公开(公告)号：US20200280121A1

公开(公告)日：2020-09-03

申请号：US16369452

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Telesphor Kamgaing ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01Q1/22 ,  H01L23/00 ,  H01L23/66 ,  H01L25/065 ,  H01L23/552 ,  H01L25/00

Abstract: Embodiments may relate to an semiconductor package. The semiconductor package may include a die coupled with the face of the package substrate. The semiconductor package may further include a waveguide coupled with the face of the package substrate adjacent to the die, wherein the waveguide is to receive an electromagnetic signal from the die and facilitate conveyance of the electromagnetic signal in a direction parallel to the face of the package substrate. Other embodiments may be described or claimed.

公开(公告)号：US20200185457A1

公开(公告)日：2020-06-11

申请号：US16635111

申请日：2017-08-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Van H. Le ,  Gilbert W. Dewey ,  Willy Rachmady

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

Abstract: Disclosed herein are selector devices and related devices and techniques. In some embodiments, a selector device may include a first electrode, a second electrode, and a selector material between the first electrode and the second electrode. The selector material may include a dielectric material and a conductive dopant.

公开(公告)号：US20200083225A1

公开(公告)日：2020-03-12

申请号：US16124877

申请日：2018-09-07

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Abhishek A. Sharma ,  Van H. Le ,  Seung Hoon Sung ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822 ,  H01L29/06 ,  H01L49/02

Abstract: Disclosed herein are memory cells and memory arrays, as well as related methods and devices. For example, in some embodiments, a memory device may include: a support having a surface; and a three-dimensional array of memory cells on the surface of the support, wherein individual memory cells include a transistor and a capacitor, and a channel of the transistor in an individual memory cell is oriented parallel to the surface.

公开(公告)号：US20200013861A1

公开(公告)日：2020-01-09

申请号：US16489660

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Gilbert W. Dewey ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack T. Kavalieros ,  Cory E. Weber

IPC: H01L29/24 ,  H01L27/108 ,  H01L29/786

Abstract: Substrates, assemblies, and techniques for a backend transistor, where the backend transistor includes a gate, a semiconductor oxide, a source metal and a drain metal, and an insulator between the source metal and the gate and between the drain metal and the gate. The insulator can allow for tunneling between the source metal and/or the drain metal and the semiconductor oxide.

公开(公告)号：US20190089036A1

公开(公告)日：2019-03-21

申请号：US16192293

申请日：2018-11-15

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Gilbert W. Dewey ,  Hyung-Jin Lee

IPC: H01P3/16 ,  H01P1/208 ,  H01L23/66

Abstract: Embodiments may relate to a dielectric waveguide that includes a substrate and a waveguide material disposed within the substrate. The dielectric waveguide may further include a waveguide launcher electromagnetically and physically coupled with the waveguide material, wherein the waveguide launcher is exposed at a side of the dielectric substrate. Other embodiments may be described or claimed.

公开(公告)号：US20240105508A1

公开(公告)日：2024-03-28

申请号：US17935647

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Jitendra Kumar Jha ,  Justin Mueller ,  Nazila Haratipour ,  Gilbert W. Dewey ,  Chi-Hing Choi ,  Jack T. Kavalieros ,  Siddharth Chouksey ,  Nancy Zelick ,  Jean-Philippe Turmaud ,  I-Cheng Tung ,  Blake Bluestein

IPC: H01L21/768 ,  H01L29/49

CPC classification number: H01L21/76856 ,  H01L21/76837 ,  H01L21/76877 ,  H01L29/4908

Abstract: Disclosed herein are integrated circuit (IC) devices with contacts using nitridized molybdenum. For example, a contact arrangement for an IC device may include a semiconductor material and a contact extending into a portion of the semiconductor material. The contact may include molybdenum. The molybdenum may be in a first layer and a second layer, where the second layer may further include nitrogen. The first layer may have a thickness between about 5 nanometers and 16 nanometers, and the second layer may have a thickness between about 0.5 nanometers to 2.5 nanometers. The contact may further include a fill material (e.g., an electrically conductive material) and the second layer may be in contact with the fill material. The molybdenum may have a low resistance, and thus may improve the electrical performance of the contact. The nitridized molybdenum may prevent oxidation during the fabrication of the contact.

公开(公告)号：US11784239B2

公开(公告)日：2023-10-10

申请号：US16341020

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Aaron D. Lilak ,  Justin R. Weber ,  Harold W. Kennel ,  Willy Rachmady ,  Gilbert W. Dewey ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/66795 ,  H01L29/0665 ,  H01L29/408 ,  H01L29/785 ,  H01L29/7855

Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

公开(公告)号：US20230187553A1

公开(公告)日：2023-06-15

申请号：US17546461

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Gilbert W. Dewey ,  Siddharth Chouksey ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B. Clendenning ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78618 ,  H01L29/78696 ,  H01L29/66742

Abstract: Described herein are integrated circuit devices with source and drain (S/D) contacts with barrier regions. The S/D contacts conduct current to and from semiconductor devices, e.g., to the source and drain regions of a transistor. The barrier regions are formed between the S/D region and an inner conductive structure and reduce the Schottky barrier height between the S/D region and the contact. The barrier regions may include one or more carbon layers and one or more metal layers. A metal layer may include niobium, tantalum, aluminum, or titanium.

公开(公告)号：US11573798B2

公开(公告)日：2023-02-07

申请号：US16290544

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow

IPC: H01L29/772 ,  G06F9/30 ,  G06F9/34 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.