公开(公告)号：US20230069054A1

公开(公告)日：2023-03-02

申请号：US17410257

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Souvik GHOSH ,  Han Wui THEN ,  Pratik KOIRALA ,  Tushar TALUKDAR ,  Paul NORDEEN ,  Nityan NAIR ,  Marko RADOSAVLJEVIC ,  Ibrahim BAN ,  Kimin JUN ,  Jay GUPTA ,  Paul B. FISCHER ,  Nicole K. THOMAS ,  Thomas HOFF ,  Samuel James BADER

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

公开(公告)号：US20220140128A1

公开(公告)日：2022-05-05

申请号：US17578847

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L29/417

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20220140127A1

公开(公告)日：2022-05-05

申请号：US17578259

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/417

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

公开(公告)号：US20220069094A1

公开(公告)日：2022-03-03

申请号：US17522764

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Patrick MORROW ,  Rishabh MEHANDRU ,  Aaron D. LILAK ,  Kimin JUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20210104435A1

公开(公告)日：2021-04-08

申请号：US17122939

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Il-Seok SON ,  Colin T. CARVER ,  Paul B. FISCHER ,  Patrick MORROW ,  Kimin JUN

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US20200273839A1

公开(公告)日：2020-08-27

申请号：US16647863

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20180151541A1

公开(公告)日：2018-05-31

申请号：US15575323

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kimin JUN ,  Jacob M. JENSEN ,  Patrick MORROW ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L24/50 ,  H01L24/86 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68322 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2224/8612 ,  H01L2224/86214 ,  H01L2224/8689 ,  H01L2224/95001 ,  H01L2225/06579

Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.

公开(公告)号：US20170077030A1

公开(公告)日：2017-03-16

申请号：US15122913

申请日：2014-09-27

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  Patrick MORROW ,  Kimin JUN

IPC: H01L23/528 ,  H01L29/78 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

Abstract translation: 一种包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连的方法，其中所述多个第二互连包括不同尺寸的互连; 以及形成与所述第二多个互连件的接触点，所述接触点可操作以连接到外部源。 一种包括在包括多个电路器件的集成电路器件层的相对侧上包括多个第一互连和多个第二互连的衬底的器件，其中所述多个第二互连包括不同尺寸的互连; 以及耦合到第二多个互连的接触点，所述接触点可操作用于连接到外部源。

公开(公告)号：US20170069598A1

公开(公告)日：2017-03-09

申请号：US15122630

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

Abstract translation: 一种包括形成第一衬底的方法，所述第一衬底包括设置在多个第一互连和多个第二互连之间的集成电路器件层; 将包括存储器件层的第二衬底耦合到所述第一衬底，使得所述存储器件层与所述多个第一互连和所述多个第二互连中的一个并置; 以及去除所述第一基板的一部分。 一种装置，包括：器件层，包括设置在基板上的多个第一互连和多个第二互连之间的多个电路器件; 存储器件层，包括并置并耦合到所述多个第一互连和所述多个第二互连中的一个的多个存储器件; 以及联接到所述第一多个互连中的一个和所述第二多个互连中的一个的接触点。

公开(公告)号：US20170069597A1

公开(公告)日：2017-03-09

申请号：US15122382

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  M. Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

Abstract translation: 一种方法，包括在衬底上形成多个第一器件和多个第一互连件; 将包括多个第二设备的第二设备层耦合到所述多个第一互连中的一个，并且在所述第二设备层上形成多个第二互连。 一种包括第一装置层的装置，包括设置在多个第一互连和多个第二互连之间的多个第一电路装置和包括多个第二装置的第二装置层，所述第二装置层并置并耦合到所述多个第一互连中的一个， 所述多个第二互连，其中所述多个第一装置和所述多个第二装置中的一个包括具有比所述多个第一装置和所述多个第二装置中的另一个更高的电压范围的装置。