公开(公告)号：US12131991B2

公开(公告)日：2024-10-29

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/4232

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US11683939B2

公开(公告)日：2023-06-20

申请号：US16396451

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Benjamin Buford ,  Angeline Smith ,  Noriyuki Sato ,  Tanay Gosavi ,  Kaan Oguz ,  Christopher Wiegand ,  Kevin O'Brien ,  Tofizur Rahman ,  Gary Allen ,  Sasikanth Manipatruni ,  Emily Walker

IPC: H10B61/00 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10B61/22 ,  H10N50/10 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80

Abstract: A memory apparatus includes a first electrode having a spin orbit material. The memory apparatus further includes a first memory device on a portion of the first electrode and a first dielectric adjacent to a sidewall of the first memory device. The memory apparatus further includes a second memory device on a portion of the first electrode and a second dielectric adjacent to a sidewall of the second memory device. A second electrode is on and in contact with a portion of the first electrode, where the second electrode is between the first memory device and the second memory device. The second electrode has a lower electrical resistance than an electrical resistance of the first electrode. The memory apparatus further includes a first interconnect structure and a second interconnect, each coupled with the first electrode.

公开(公告)号：US20230092244A1

公开(公告)日：2023-03-23

申请号：US17481760

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Hui Jae Yoo ,  Van H. Le ,  Sarah Atanasov ,  Abhishek A. Sharma

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: Described herein are back-gated transistors with fin-shaped gates, and IC devices including such transistors. The transistor includes a gate electrode formed over a support structure, where the gate electrode includes a metal fin that extends perpendicular to the support structure. A gate dielectric formed of a metal oxide film is deposited over the gate electrode and conforming to the fin shape, and a channel material formed of a high mobility oxide semiconductor film is deposited over the gate dielectric, the channel material also conforming to the fin shape. Source and drain contacts may be arranged so that the fin creates a channel with a larger channel width or a longer channel length.

公开(公告)号：US20220352068A1

公开(公告)日：2022-11-03

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11444237B2

公开(公告)日：2022-09-13

申请号：US16024393

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Gary Allen ,  Sasikanth Manipatruni ,  Kaan Oguz ,  Kevin O'Brien ,  Christopher Wiegand ,  Angeline Smith ,  Tofizur Rahman ,  Ian Young ,  Ben Buford

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  G11C11/14

Abstract: A spin orbit torque (SOT) memory device includes a SOT electrode having a spin orbit coupling material. The SOT electrode has a first sidewall and a second sidewall opposite to the first sidewall. The SOT memory device further includes a magnetic tunnel junction device on a portion of the SOT electrode. A first MTJ sidewall intersects the first SOT sidewall and a portion of the first MTJ sidewall and the SOT sidewall has a continuous first slope. The MTJ device has a second sidewall that does not extend beyond the second SOT sidewall and at least a portion of the second MTJ sidewall has a second slope.

公开(公告)号：US11444024B2

公开(公告)日：2022-09-13

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11430943B2

公开(公告)日：2022-08-30

申请号：US16022561

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01L43/12 ,  H01F41/30 ,  H01L27/22 ,  H01L43/10

Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.

公开(公告)号：US11417830B2

公开(公告)日：2022-08-16

申请号：US16024709

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Gary Allen ,  Kaan Oguz ,  Kevin O'Brien ,  Noriyuki Sato ,  Ian Young ,  Dmitri Nikonov

IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12 ,  H01L43/10

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

公开(公告)号：US11374164B2

公开(公告)日：2022-06-28

申请号：US16024714

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Tanay Gosavi ,  Sasikanth Manipatruni ,  Chia-Ching Lin ,  Kaan Oguz ,  Christopher Wiegand ,  Angeline Smith ,  Noriyuki Sato ,  Kevin O'Brien ,  Benjamin Buford ,  Ian Young ,  Md Tofizur Rahman

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Embodiments herein relate to a system, apparatus, and/or process for producing a spin orbit torque (SOT) electrode that includes a first layer with a first side to couple with a free layer of a magnetic tunnel junction (MTJ) and a second layer coupled with a second side of the first layer opposite the first side, where a value of an electrical resistance in the first SOT layer is lower than a value of an electrical resistance in the second SOT layer and where a current applied to the SOT electrode is to cause current to preferentially flow in the first SOT layer to cause a magnetic polarization of the free layer to change directions. During production of the SOT electrode, the second layer may act as an etch stop.

公开(公告)号：US20220190121A1

公开(公告)日：2022-06-16

申请号：US17121313

申请日：2020-12-14

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Arnab Sen Gupta ,  Matthew V. Metz ,  Hui Jae Yoo

IPC: H01L29/26 ,  H01L29/786

Abstract: Disclosed herein are transistor channel materials, and related methods and devices. For example, in some embodiments, a transistor may include a channel material including a semiconductor material having a first conductivity type, and the channel material may further include a dopant including (1) an insulating material and/or (2) a material having a second conductivity type opposite to the first conductivity type.