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公开(公告)号：US09760162B2
公开(公告)日：2017-09-12
申请号：US14033008
申请日：2013-09-20
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F9/00 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US11366511B2
公开(公告)日：2022-06-21
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US11054890B2
公开(公告)日：2021-07-06
申请号：US13954980
申请日：2013-07-31
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
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Patent Agency Ranking
公开(公告)号：US11018264B1
公开(公告)日：2021-05-25
申请号：US16715135
申请日：2019-12-16
Applicant: Intel Corporation
Inventor： Wilfred Gomes , Kinyip Phoa , Tahir Ghani , Rajesh Kumar
IPC: H01L29/786 , H01L29/423 , H01L21/8234 , H01L23/535 , H01L27/088
Abstract: Described herein are three-dimensional nanoribbon-based logic ICs that include one of more of 1) individual gate control in a vertical stack of nanoribbons, 2) inter-ribbon interconnects in a vertical stack of nanoribbons, and 3) both P- and N-type nanoribbons in a vertical stack of nanoribbons. Using one or more of these features may help realize unique monolithic 3D logic architectures that were not possible with conventional logic circuits and may allow realizing logic devices with favorable metrics in terms of power and performance while preserving the substrate area and cost.
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公开(公告)号：US20210089113A1
公开(公告)日：2021-03-25
申请号：US17115604
申请日：2020-12-08
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
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公开(公告)号：US10386915B2
公开(公告)日：2019-08-20
申请号：US15256006
申请日：2016-09-02
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/24 , G06F9/00 , G06F1/3293 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06T1/20 , G06F1/3206 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/3228 , G06F1/20 , G06F1/3287 , G06F12/0875
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09910483B2
公开(公告)日：2018-03-06
申请号：US14154517
申请日：2014-01-14
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F9/30 , G06F1/32 , G06T1/20 , G06F9/50 , G06F13/24 , G06F9/38 , G06F9/46 , G06F1/20 , G06F12/0875
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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公开(公告)号：US09874926B2
公开(公告)日：2018-01-23
申请号：US14498319
申请日：2014-09-26
Applicant: Intel Corporation
Inventor： Herbert Hum , Eric Sprangle , Douglas Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
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