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    CRYSTALLINE BOTTOM ELECTRODE FOR PEROVSKITE CAPACITORS AND METHODS OF FABRICATION
    31.
    发明申请
    CRYSTALLINE BOTTOM ELECTRODE FOR PEROVSKITE CAPACITORS AND METHODS OF FABRICATION 有权

    公开(公告)号：US20210408224A1

    公开(公告)日：2021-12-30

    申请号：US16914161

    申请日：2020-06-26

    Applicant: Intel Corporation

    Inventor： Kaan Oguz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Matthew Metz ,  Uygar Avci

    IPC: H01L49/02 ,  H01L27/06

    Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

    Memory devices based on capacitors with built-in electric field
    32.
    发明授权
    Memory devices based on capacitors with built-in electric field 有权

    公开(公告)号：US11171145B2

    公开(公告)日：2021-11-09

    申请号：US16016375

    申请日：2018-06-22

    Applicant: Intel Corporation

    Inventor： Sou-Chi Chang ,  Uygar Avci ,  Daniel H. Morris ,  Seiyon Kim ,  Ashish V. Penumatcha ,  Ian A. Young

    IPC: H01L27/115 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22

    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

    Memory including a perovskite material
    35.
    发明授权
    Memory including a perovskite material 有权

    公开(公告)号：US10861861B2

    公开(公告)日：2020-12-08

    申请号：US16221083

    申请日：2018-12-14

    Applicant: Intel Corporation

    Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Sou-Chi Chang ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/11509 ,  H01L27/11592

    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

    IMPROPER FERROELECTRIC ACTIVE AND PASSIVE DEVICES
    36.
    发明申请
    IMPROPER FERROELECTRIC ACTIVE AND PASSIVE DEVICES 审中-公开

    公开(公告)号：US20200091308A1

    公开(公告)日：2020-03-19

    申请号：US16130903

    申请日：2018-09-13

    Applicant: Intel Corporation

    Inventor： Sasikanth Manipatruni ,  Uygar Avci ,  Sou-Chi Chang ,  Ian Young

    IPC: H01L29/51 ,  H01L29/78 ,  H01L27/11502 ,  H01L27/11585 ,  G11C11/22

    Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

    SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS
    39.
    发明申请
    SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS 有权

    公开(公告)号：US20250008740A1

    公开(公告)日：2025-01-02

    申请号：US18216490

    申请日：2023-06-29

    Applicant: Intel Corporation

    Inventor： Wriddhi Chakraborty ,  Sourav Dutta ,  Nazila Haratipour ,  Sou-Chi Chang ,  Shriram Shivaraman ,  Gilbert Dewey ,  Uygar Avci

    IPC: H10B53/20 ,  H10B53/30

    Abstract: An integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. The storage material may be a ferroelectric material. A gate dielectric of the access transistor may be around, and coaxial with, a channel region. The channel region may be vertically oriented and coaxial with the first electrode. A second access transistor may be similarly aligned with the first electrode and the stack of capacitors with the capacitor stack between the transistors. A channel of the second transistor may be around, and coaxial with, a gate dielectric. The transistors and capacitor stack may be in arrays of transistors and capacitor stacks. A self-aligned process may be used to form the capacitor and transistor arrays.

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