公开(公告)号：US11594637B2

公开(公告)日：2023-02-28

申请号：US16833208

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Stephen Snyder ,  Biswajeet Guha ,  William Hsu ,  Urusa Alaan ,  Tahir Ghani ,  Michael K. Harper ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10

Abstract: Gate-all-around integrated circuit structures having fin stack isolation, and methods of fabricating gate-all-around integrated circuit structures having fin stack isolation, are described. For example, an integrated circuit structure includes a sub-fin structure on a substrate, the sub-fin structure having a top and sidewalls. An isolation structure is on the top and along the sidewalls of the sub-fin structure. The isolation structure includes a first dielectric material surrounding regions of a second dielectric material. A vertical arrangement of horizontal nanowires is on a portion of the isolation structure on the top surface of the sub-fin structure.

公开(公告)号：US11164790B2

公开(公告)日：2021-11-02

申请号：US16632319

申请日：2017-08-17

Applicant: Intel Corporation

Inventor： Leonard P Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US20200176321A1

公开(公告)日：2020-06-04

申请号：US16632319

申请日：2017-08-17

Applicant: Intel Corporation

Inventor： Leonard P/ Guler ,  Biswajeet Guha ,  Mark Armstrong ,  Tahir Ghani ,  William Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/308

Abstract: Fabrication of narrow and wide structures based on lithographic patterning of exclusively narrow mask structures. Multi-patterning may be employed to define narrow mask structures. Wide mask structures may be derived through a process-based merging of multiple narrow mask structures. The merge may include depositing a cap layer over narrow structures, filling in minimum spaces. The cap layer may be removed leaving residual cap material only within minimum spaces. Narrow and wide structures may be etched into an underlayer based on a summation of the narrow mask structures and residual cap material. A plug pattern may further mask portions of the cap layer not completely filling space between adjacent mask structures. The underlayer may then be etched based on a summation of the narrow mask structures, plug pattern, and residual cap material. Such methods may be utilized to integrate nanoribbon transistors with nanowire transistors in an integrated circuit (IC).

公开(公告)号：US20200044087A1

公开(公告)日：2020-02-06

申请号：US16055634

申请日：2018-08-06

Applicant: INTEL CORPORATION

Inventor： Biswajeet Guha ,  William Hsu ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: Sub-fin isolation schemes for gate-all-around (GAA) transistor devices are provided herein. In some cases, the sub-fin isolation schemes include forming one or more dielectric layers between each of the source/drain regions and the substrate. In some such cases, the one or more dielectric layers include material native to the gate sidewall spacers, for example, or other dielectric material. In other cases, the sub-fin isolation schemes include substrate modification that results in oppositely-type doped semiconductor material under each of the source/drain regions and in the sub-fin. The oppositely-type doped semiconductor material results in the interface between that material and each of the source/drain regions being a p-n or n-p junction to block the flow of carriers through the sub-fin. The various sub-fin isolation schemes described herein enable better short channel characteristics for GAA transistors (e.g., employing one or more nanowires, nanoribbons, or nanosheets), thereby improving device performance.

公开(公告)号：US20190393351A1

公开(公告)日：2019-12-26

申请号：US16015404

申请日：2018-06-22

Applicant: INTEL CORPORATION

Inventor： Bruce E. Beattie ,  Leonard Guler ,  Biswajeet Guha ,  Jun Sung Kang ,  William Hsu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-κ”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.

公开(公告)号：US20240088296A1

公开(公告)日：2024-03-14

申请号：US18514974

申请日：2023-11-20

Applicant: Intel Corporation

Inventor： Erica J. THOMPSON ,  Aditya Kasukurti ,  Jun Sung Kang ,  Kai Loon Cheong ,  Biswajeet Guha ,  William Hsu ,  Bruce Beattie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7855 ,  H01L21/02238

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11705518B2

公开(公告)日：2023-07-18

申请号：US17722142

申请日：2022-04-15

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen M. Cea ,  Biswajeet Guha ,  Tahir Ghani ,  William Hsu

IPC: H01L29/78 ,  H01L21/761 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7846 ,  H01L21/761 ,  H01L21/762 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/66553 ,  H01L29/7853

Abstract: Isolation schemes for gate-all-around (GAA) transistor devices are provided herein Integrated circuit structures including increased transistor source/drain contact area using a sacrificial source/drain layer are provided herein. In some cases, the isolation schemes include changing the semiconductor nanowires/nanoribbons in a targeted channel region between active or functional transistor devices to electrically isolate those active devices. The targeted channel region is referred to herein as a dummy channel region, as it is not used as an actual channel region for an active or functional transistor device. The semiconductor nanowires/nanoribbons in the dummy channel region can be changed by converting them to an electrical insulator and/or by adding dopant that is opposite in type relative to surrounding source/drain material (to create a p-n junction). The isolation schemes described herein enable neighboring active devices to retain strain in the nanowires/nanoribbons of their channel regions, thereby improving device performance.

公开(公告)号：US20230197818A1

公开(公告)日：2023-06-22

申请号：US17559342

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  William Hsu ,  Mohammad Hasan ,  Ritesh Das ,  Vivek Thirtha ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

公开(公告)号：US11569370B2

公开(公告)日：2023-01-31

申请号：US16454408

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar ,  Biswajeet Guha ,  William Hsu ,  Dax Crum ,  Oleg Golonzka ,  Tahir Ghani ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.