公开(公告)号：US20230187284A1

公开(公告)日：2023-06-15

申请号：US17551266

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ruturaj Nandkumar Pujari ,  Ashim Dutta ,  Chih-Chao Yang

IPC: H01L21/66 ,  H01L21/67

CPC classification number: H01L22/12 ,  H01L21/67253 ,  H01L22/26 ,  H01L22/34

Abstract: Embodiments of the present invention are directed to in-situ wafer feedback schemes and systems for providing localized process-based compensation on a semiconductor wafer. In a non-limiting embodiment of the invention, a plurality of test structures are formed on a surface of a semiconductor wafer. The semiconductor wafer is placed under a detection surface of an in-situ feedback tool comprising one or more sensors. The in-situ feedback tool measures a property of each of the plurality of test structures and determines a local condition of the semiconductor wafer for each measured property of the plurality of test structures. A localized process-based compensation is provided on the surface of the semiconductor wafer for each local condition.

公开(公告)号：US20230178588A1

公开(公告)日：2023-06-08

申请号：US17457747

申请日：2021-12-06

Applicant: International Business Machines Corporation

Inventor： CHANRO PARK ,  Koichi Motoyama ,  Kenneth Chun Kuen Cheng ,  Chih-Chao Yang

IPC: H01L49/02

CPC classification number: H01L28/92 ,  H01L28/91

Abstract: A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

公开(公告)号：US20230178423A1

公开(公告)日：2023-06-08

申请号：US17457444

申请日：2021-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53266 ,  H01L21/76843

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines and one or more top vias in direct contact with a top surface of the one or more metal lines. The interconnect structure also includes a liner formed on sidewalls of the one or more top vias and top portions of the one or more metal lines.

公开(公告)号：US20230170298A1

公开(公告)日：2023-06-01

申请号：US17457048

申请日：2021-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Ruilong Xie ,  Tsung-Sheng Kang ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/528 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/76802 ,  H01L21/76224 ,  H01L21/76819

Abstract: An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes one or more metal lines in direct contact with a top surface of one or more devices and one or more vias in direct contact with top surfaces of the one or more metal lines. The interconnect structure also includes one or more dielectric pillars in direct contact with the top surface of the one or more devices. A height of a top surface of the one or more dielectric pillars above the one or more devices is equal to a height of a top surface of the one or more vias above the one or more devices.

公开(公告)号：US20230157181A1

公开(公告)日：2023-05-18

申请号：US17455226

申请日：2021-11-17

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

Abstract: An approach to provide a pillar-type memory device with a bump of a conductive material on a top electrode of the pillar-type memory device. The top electrode is composed of a thin layer of the top electrode material. The bump of the conductive material increases the height of the top electrode after pillar formation for the pillar-type memory device. The pillar-type memory device includes the bump of the conductive material with a semi-sphere-like bump of the conductive metal that is slightly wider than the top electrode of the pillar-type memory device. A contact connects with the bump of the conductive material on the top electrode.

公开(公告)号：US20230144157A1

公开(公告)日：2023-05-11

申请号：US17520672

申请日：2021-11-07

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  Oscar van der Straten ,  Joseph F. Maniscalco ,  Chih-Chao Yang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A first set of spacers are formed on the sidewalls of a bottom electrode. A reference layer is formed on the spacers and the bottom electrode. A second set of spacers are formed on the sidewalls of the first set of spacers and the reference layer. A tunnel barrier is formed on the reference layer and the second set of spacers. A free layer is formed on the tunnel barrier, where a width of the free layer is greater than a width of the reference layer. A metal hardmask is formed on the free layer. A third set of spacers are formed on the sidewalls of the metal hardmask, the free layer, the tunnel barrier, and the second set of spacers.

公开(公告)号：US20230120199A1

公开(公告)日：2023-04-20

申请号：US17493884

申请日：2021-10-05

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  CHANRO PARK ,  Kenneth Chun Kuen Cheng ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

Abstract: A copper interconnect with an embedded dielectric cap between lines comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a first dielectric cap formed between each interconnect line of the plurality of interconnect lines. The copper interconnect further comprises a second dielectric cap formed on top of the plurality of interconnect lines and the first dielectric cap, wherein the second dielectric cap formed on top of the first dielectric cap forms a bi-layer dielectric cap between the plurality of interconnect lines.

公开(公告)号：US20230110587A1

公开(公告)日：2023-04-13

申请号：US17450470

申请日：2021-10-11

Applicant: International Business Machines Corporation

Inventor： Koichi Motoyama ,  CHANRO PARK ,  Kenneth Chun Kuen Cheng ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/00

Abstract: A copper interconnect with self-aligned hourglass-shaped metal cap comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a metal cap formed on top of each interconnect line of the plurality of interconnect lines, where the metal cap is formed with self-aligning concave sides extending from a top surface of the dielectric layer to a top surface of the metal cap.

公开(公告)号：US20230086420A1

公开(公告)日：2023-03-23

申请号：US17479660

申请日：2021-09-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Chanro Park ,  Koichi Motoyama ,  Chih-Chao Yang

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/532 ,  H01L23/522

Abstract: Methods for forming conductive lines and integrated chips include forming a mandrel on an etch stop layer. First spacers are formed on sidewalls of the mandrel. The mandrel is etched away. Conductive lines are formed on sidewalls of the first spacers. The first spacers are etched away. Dielectric spacers are formed between the conductive lines.

公开(公告)号：US20230081953A1

公开(公告)日：2023-03-16

申请号：US17447586

申请日：2021-09-14

Applicant: International Business Machines Corporation

Inventor： Saumya Sharma ,  Ashim Dutta ,  Tianji Zhou ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/768

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.