公开(公告)号：US20230094466A1

公开(公告)日：2023-03-30

申请号：US17486840

申请日：2021-09-27

Applicant: International Business Machines Corporation

Inventor： Julien Frougier ,  Nicolas Loubet ,  Sagarika Mukesh ,  PRASAD BHOSALE ,  Ruilong Xie ,  Andrew Herbert Simon ,  Takeshi Nogami ,  Lawrence A. Clevenger ,  Roy R. Yu ,  Andrew M. Greene ,  Daniel Charles Edelstein

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.

公开(公告)号：US11557482B2

公开(公告)日：2023-01-17

申请号：US16593392

申请日：2019-10-04

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Chao-Kun Hu ,  Oscar van der Straten

IPC: H01L21/24 ,  H01L21/324 ,  H01L21/04 ,  H01L21/304 ,  H01L21/768

Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

公开(公告)号：US11302630B2

公开(公告)日：2022-04-12

申请号：US16842951

申请日：2020-04-08

Applicant: International Business Machines Corporation

Inventor： Theodorus E. Standaert ,  Chih-Chao Yang ,  Daniel Charles Edelstein

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/321 ,  H01L43/12

Abstract: A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure.

公开(公告)号：US20210104406A1

公开(公告)日：2021-04-08

申请号：US16593392

申请日：2019-10-04

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Chao-Kun Hu ,  Oscar Van der Straten

IPC: H01L21/24 ,  H01L21/324 ,  H01L21/768 ,  H01L21/304 ,  H01L21/04

Abstract: An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

公开(公告)号：US09824917B2

公开(公告)日：2017-11-21

申请号：US15496172

申请日：2017-04-25

Applicant: International Business Machines Corporation

Inventor： Chih-chao Yang ,  Daniel Charles Edelstein

IPC: H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76834 ,  C23C16/45544 ,  C23C16/50 ,  H01L21/3212 ,  H01L21/67098 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/1087

Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.

公开(公告)号：US09702042B1

公开(公告)日：2017-07-11

申请号：US15352917

申请日：2016-11-16

Applicant: International Business Machines Corporation

Inventor： Chih-chao Yang ,  Daniel Charles Edelstein

IPC: H01L21/768 ,  C23C16/455 ,  C23C16/50 ,  H01L27/108 ,  H01L21/67

CPC classification number: H01L21/76834 ,  C23C16/45544 ,  C23C16/50 ,  H01L21/3212 ,  H01L21/67098 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/1087

Abstract: The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many include forming a via to expose several layers of a microchip. The layers may include, pattered dielectric layer, a capping layer, a first metal layer and an insulator. A surface modification step is then implemented to modify and/or densify the treated surfaces of the dielectric surface. A metal compound removal step is then implemented to remove metal compounds from the bottom of the via. Finally, the via is filled with a conductive material. The surface modification and the metal compound removal steps are implemented in one chamber.