公开(公告)号：US20150032968A1

公开(公告)日：2015-01-29

申请号：US13950371

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Philip Heidelberger ,  Hillery C. Hunter ,  James A. Kahle ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/126 ,  G06F2212/1024 ,  G06F2212/154 ,  G06F2212/604

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract translation: 一种用于在存储器系统中实现存储器层级放置决策的方法，系统和存储器控制器，包括将到达数据直接路由到主存储器系统中，并且将数据或计算结果选择性地注入计算机系统中的处理器高速缓存。 存储器控制器或存储器系统中的处理元件选择性地将数据放置到存储器层级的其他级别中。 注入层次结构的决定可以通过来自输入输出（IO）设备的数据到来自计算或来自存储器内处理元件的指令来触发。

公开(公告)号：US20140195743A1

公开(公告)日：2014-07-10

申请号：US13737339

申请日：2013-01-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F13/18

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0673 ,  G06F9/4881 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/18 ,  Y02D10/14

Abstract: According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

Abstract translation: 根据一个实施例，一种用于存储器设备中的业务优先级排序的方法包括：将存储器设备中的处理元件中包含优先级值的存储器访问请求发送到存储器设备中的交叉连接。 存储器访问请求通过交叉开关互连路由到与存储器访问请求相关联的存储器设备中的存储器控​​制器。 存储器访问请求在存储器控制器处被接收。 将存储器访问请求的优先级值与存储在存储器控制器的队列中的多个存储器访问请求的优先级值进行比较，以确定最高优先级的存储器访问请求。 存储器控制器基于最高优先级的存储器访问请求来执行下一个存储器访问请求。

公开(公告)号：US20140149673A1

公开(公告)日：2014-05-29

申请号：US13787057

申请日：2013-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  Y02D10/13

Abstract: According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue.

公开(公告)号：US20140136895A1

公开(公告)日：2014-05-15

申请号：US13677746

申请日：2012-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce M. Fleischer ,  Thomas W. Fox ,  Hans M. Jacobson ,  Ravi Nair

IPC: G06F11/14

CPC classification number: G06F11/14 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/3863 ,  G06F9/3877 ,  G06F9/3887 ,  G06F11/1405 ,  G06F12/10 ,  Y02D10/13

Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.

Abstract translation: 一个方面包括在暴露流水线处理元件中提供回滚支持。 系统包括具有回滚支持逻辑的暴露流水线处理元件。 回滚支持逻辑被配置为检测与暴露流水线处理元件中的指令的执行相关联的错误。 回滚支持逻辑确定暴露流水线处理元件是否支持指令预定次数循环的重放。 基于确定暴露流水线处理元件支持指令的重放，在暴露流水线处理元件中执行回滚动作以尝试从错误中恢复。

公开(公告)号：US20240029786A1

公开(公告)日：2024-01-25

申请号：US17814254

申请日：2022-07-22

Applicant: International Business Machines Corporation

Inventor： Ravi Nair ,  Swagath Venkataramani ,  Vijayalakshmi Srinivasan ,  Arvind Kumar

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C5/06

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C5/06

Abstract: A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.

公开(公告)号：US11288208B2

公开(公告)日：2022-03-29

申请号：US16218118

申请日：2018-12-12

Applicant: International Business Machines Corporation

Inventor： Ravi Nair ,  Charles R. Johns ,  James A. Kahle ,  Changhoan Kim ,  Constantinos Evangelinos ,  Patrick D. Siegl

IPC: G06F12/1072 ,  G06F12/0817 ,  G06F12/02 ,  G06F9/54 ,  G06F12/1018 ,  G06F13/16 ,  G06F12/06

Abstract: An approach is described that provides access to a named data element in a Coordination Namespace that is stored in a memory that is distributed amongst a set of nodes. A request of a name corresponding to the named data element is received from a requesting process and the approach responsively searches for the name in the Coordination Namespace. In response to determining an absence of data corresponding to the named data element, a pending state is indicated to the requesting process. In response to determining that the data corresponding to the named data element exists, a successful state is returned to the requesting process. In one embodiment, the successful state also includes providing the requesting process with access to the data corresponding to the named data element.

公开(公告)号：US11275614B2

公开(公告)日：2022-03-15

申请号：US16586185

申请日：2019-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Harold W. Cain, III ,  Hubertus Franke ,  Charles R. Johns ,  Hung Q. Le ,  Ravi Nair ,  James A. Kahle

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.

公开(公告)号：US20220012741A1

公开(公告)日：2022-01-13

申请号：US16923295

申请日：2020-07-08

Applicant: International Business Machines Corporation

Inventor： Jeetu Raj ,  Erik Richter Altman ,  Shyam Ramji ,  Ravi Nair

IPC: G06Q20/40 ,  G06N20/00

Abstract: Application of multi-task learning technique(s) to machine logic (for example, software) used to detect financial transactions that are fraudulent or at least considered likely to be fraudulent. Some embodiments include adjustments and/or additions to conventional multi-task learning techniques in order to make the multi-task learning techniques more suitable for use in fraud detection software. One example of this is compensation for class imbalances that are to be expected as between the likely-fraud and not-likely-fraud classes of data sets (for example, training data sets, runtime data sets).

公开(公告)号：US11068612B2

公开(公告)日：2021-07-20

申请号：US16051719

申请日：2018-08-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prashant J. Nair ,  Seokin Hong ,  Alper Buyuktosunoglu ,  Ravi Nair

IPC: G06F12/0842 ,  G06F12/0893 ,  G06F21/62 ,  G06F12/0802 ,  G06F12/14

Abstract: Embodiments for mitigating cache-based data security vulnerabilities in a computing environment are provided. Cache pollution due to speculative memory accesses within a speculative path is avoided by delaying data updates to a cache and memory subsystem until the speculative memory accesses are resolved. A speculative buffer is used to maintain the speculative memory accesses such that a state of the cache remains unchanged until the speculative memory accesses are committed.

公开(公告)号：US20200327445A1

公开(公告)日：2020-10-15

申请号：US16379192

申请日：2019-04-09

Applicant: International Business Machines Corporation

Inventor： Yang Yu ,  Ming Tan ,  Ravi Nair ,  Haoyu Wang ,  Saloni Potdar

IPC: G06N20/00 ,  G06F16/35

Abstract: A method of text classification includes generating a text embedding vector representing a text sample and applying weights of a regression layer to the text embedding vector to generate a first data model output vector. The method also includes generating a plurality of prototype embedding vectors associated with a respective classification labels and comparing the plurality of prototype embedding vectors to the text embedding vector to generate a second data model output vector. The method further includes assigning a particular classification label to the text sample based on the first data model output vector, the second data model output vector, and one or more weighting values