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公开(公告)号:US20200013680A1
公开(公告)日:2020-01-09
申请号:US16516693
申请日:2019-07-19
Applicant: Intel Corporation
Inventor: Jeffrey S. LEIB , Srijit MUKHERJEE , Vinay BHAGWAT , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/8238 , H01L49/02 , H01L21/762 , H01L21/8234 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/78 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
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32.
公开(公告)号:US20190164968A1
公开(公告)日:2019-05-30
申请号:US15859355
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Jeffrey S. LEIB , Jenny HU , Anindya DASGUPTA , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L27/092 , H01L29/78 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/66 , H01L21/308 , H01L27/088 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L49/02
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.
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33.
公开(公告)号:US20190164897A1
公开(公告)日:2019-05-30
申请号:US15859416
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Joseph STEIGERWALD , Jinhong SHIN , Vinay CHIKARMANE , Christopher P. AUTH
IPC: H01L23/532 , H01L23/528 , H01L23/522 , H01L21/8234 , H01L27/088
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
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公开(公告)号:US20190164890A1
公开(公告)日:2019-05-30
申请号:US15859415
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Atul MADHAVAN , Christopher P. AUTH
IPC: H01L23/528 , H01L29/78 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L49/02
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.
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公开(公告)号:US20190164846A1
公开(公告)日:2019-05-30
申请号:US15859357
申请日:2017-12-30
Applicant: Intel Corporation
Inventor: Jeffrey S. LEIB , Srijit MUKHERJEE , Vinay BHAGWAT , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/8238 , H01L29/78 , H01L21/762 , H01L21/8234 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L49/02
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
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公开(公告)号:US20190164808A1
公开(公告)日:2019-05-30
申请号:US15859286
申请日:2017-12-29
Applicant: Intel Corporation
Inventor: Michael L. HATTENDORF , Curtis WARD , Heidi M. MEYER , Tahir GHANI , Christopher P. AUTH
IPC: H01L21/762 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L21/311 , H01L29/08 , H01L27/11 , H01L29/66 , H01L21/308 , H01L27/092 , H01L29/51 , H01L21/285 , H01L21/28 , H01L21/033 , H01L21/768 , H01L23/532 , H01L23/522 , H01L23/528 , H01L49/02
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.
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37.
公开(公告)号:US20250022939A1
公开(公告)日:2025-01-16
申请号:US18900094
申请日:2024-09-27
Applicant: Intel Corporation
Inventor: Andrew W. YEOH , Tahir GHANI , Atul MADHAVAN , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L29/66 , H01L21/02 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/00 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/167 , H01L29/417 , H01L29/51 , H01L29/78 , H10B10/00
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.
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公开(公告)号:US20240105520A1
公开(公告)日:2024-03-28
申请号:US18534219
申请日:2023-12-08
Applicant: Intel Corporation
Inventor: Anthony ST. AMOUR , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L21/8234 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/088 , H01L27/092 , H01L29/08 , H01L29/417 , H01L29/51 , H01L29/66 , H01L29/78 , H10B10/00
CPC classification number: H01L21/823475 , H01L21/0337 , H01L21/28247 , H01L21/28568 , H01L21/3086 , H01L21/31105 , H01L21/31144 , H01L21/76224 , H01L21/76816 , H01L21/823431 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L27/0886 , H01L27/0924 , H01L28/24 , H01L29/0847 , H01L29/41791 , H01L29/516 , H01L29/6653 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785 , H01L29/7854 , H10B10/12
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
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公开(公告)号:US20230232605A1
公开(公告)日:2023-07-20
申请号:US18124936
申请日:2023-03-22
Applicant: Intel Corporation
Inventor: Tahir GHANI , Byron HO , Curtis W. WARD , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H10B10/00 , H01L29/66 , H01L27/092 , H01L27/06
CPC classification number: H10B10/15 , H10B10/125 , H01L29/66545 , H01L27/0924 , H01L27/0688
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
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公开(公告)号:US20230131757A1
公开(公告)日:2023-04-27
申请号:US18088461
申请日:2022-12-23
Applicant: Intel Corporation
Inventor: Byron HO , Michael L. HATTENDORF , Christopher P. AUTH
IPC: H01L29/66 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/06 , H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/165 , H01L29/417 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/8238 , H01L23/528 , H01L27/092 , H10B10/00 , H01L29/08 , H01L29/51 , H01L27/02 , H01L21/02 , H01L29/167
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
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