公开(公告)号：US10163777B2

公开(公告)日：2018-12-25

申请号：US15476905

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Seok Ling Lim ,  Eng Huat Goh ,  Hoay Tien Teoh ,  Jenny Shio Yin Ong ,  Jia Yan Go ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/043

Abstract: Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.

公开(公告)号：US12191281B2

公开(公告)日：2025-01-07

申请号：US17348802

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Yang Liang Poh ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure is directed to semiconductor packages, and methods for making them, which includes a substrate with a top surface and a bottom surface, a substrate recess in the bottom surface of the substrate, a first device positioned over the top surface of the substrate, which has the first device at least partially overlapping the substrate recess, a mold material in the substrate recess, which has the mold material overlapping the bottom surface of the substrate adjacent to the substrate recess, a second device positioned in the substrate recess, and a plurality of interconnect vias in the substrate, which has at least one of the plurality interconnect vias coupled to the first and second devices to provide a direct signal connection therebetween that minimizes signal latency.

公开(公告)号：US12002747B2

公开(公告)日：2024-06-04

申请号：US17680489

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/50 ,  H01G4/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01G4/1272 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L28/60

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

公开(公告)号：US20230420379A1

公开(公告)日：2023-12-28

申请号：US17848059

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Seok Ling Lim ,  Hazwani Jaffar ,  Yean Ling Soon

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L24/08

Abstract: IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

公开(公告)号：US11562954B2

公开(公告)日：2023-01-24

申请号：US16912619

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Jenny Shio Yin Ong ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L29/00 ,  H01L29/76 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: Disclosed embodiments include frame-array interconnects that have a ledge portion to accommodate a passive device. A seated passive device is between at least two frame-array interconnects for semiconductor package-integrated decoupling capacitors.

公开(公告)号：US11527467B2

公开(公告)日：2022-12-13

申请号：US17089749

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Kooi Chi Ooi

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/552

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

公开(公告)号：US20220392835A1

公开(公告)日：2022-12-08

申请号：US17680489

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Kooi Chi Ooi ,  Jackson Chung Peng Kong

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L49/02 ,  H01G4/12 ,  H01L25/065

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.

公开(公告)号：US11462488B2

公开(公告)日：2022-10-04

申请号：US17090926

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong

IPC: H01L23/00 ,  H01L23/14 ,  H01L21/48 ,  H01L23/498 ,  H01L23/16

Abstract: According to the various aspects, a package substrate with a heterogeneous substrate core including a first core layer that is coextensive with the package substrate and extends through a first section and a second section of the substrate core, in which the first section is adjacent to and thicker than the second section. The first section having at least a second layer and/or a third layer to provide the difference in thickness with the second section.

公开(公告)号：US11430764B2

公开(公告)日：2022-08-30

申请号：US17024056

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/66

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor article having a package substrate, a first semiconductor die coupled to the package substrate, a second semiconductor die coupled to the package substrate and adjacent the first semiconductor die, and a bridge component therebetween coupling the first semiconductor die to the second semiconductor die. The bridge component can include a bridge substrate, a conductive trace therein, and a passive component coupled to the conductive trace.

公开(公告)号：US11367673B2

公开(公告)日：2022-06-21

申请号：US17089750

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong

IPC: H01L23/49 ,  H01L23/498 ,  H01L21/48 ,  H01L21/768 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00

Abstract: According to various examples, a device is described. The device may include an interposer. The device may also include a plurality of first through-silicon-vias disposed in the interposer, wherein the plurality of first through-silicon-vias have a first diameter. The device may also include a plurality of second through-silicon-vias disposed in the interposer, wherein the plurality of second through-silicon-vias have a second diameter larger than the first via diameter. The device may also include a first recess in the interposer positioned at bottom ends of the plurality of second through-silicon-vias.