公开(公告)号：US10856454B2

公开(公告)日：2020-12-01

申请号：US16535766

申请日：2019-08-08

申请人： Intel Corporation

发明人： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC分类号： H05K9/00 ,  H05K3/46 ,  H05K1/11

摘要： Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.

公开(公告)号：US20190103358A1

公开(公告)日：2019-04-04

申请号：US15845336

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC分类号： H01L23/538 ,  H05K1/18 ,  H01L25/18 ,  H01L25/00

摘要： An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US10163777B2

公开(公告)日：2018-12-25

申请号：US15476905

申请日：2017-03-31

申请人： INTEL CORPORATION

发明人： Seok Ling Lim ,  Eng Huat Goh ,  Hoay Tien Teoh ,  Jenny Shio Yin Ong ,  Jia Yan Go ,  Jiun Hann Sir ,  Min Suet Lim

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/043

摘要： Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.

公开(公告)号：US20180324951A1

公开(公告)日：2018-11-08

申请号：US15774863

申请日：2015-11-13

申请人： Intel Corporation

发明人： Penang Goh ,  Hoay Tien Teoh ,  Jia Yan Go ,  Jenny Shio Yin Ong

IPC分类号： H05K1/18 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L25/105 ,  H01L2224/81203 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/34 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/613

摘要： The electronic assembly includes a printed circuit board; an electronic package that includes an electronic component mounted on a substrate, wherein the substrate is mounted to the printed circuit board; a first memory module mounted to the printed circuit board such that the first memory module is adjacent to the electronic package; a second memory module mounted to the printed circuit board; and a substrate bridge that electrically connects the first and second memory modules to the electronic package, wherein a lower surface of the substrate bridge is connected to an upper surface of the substrate and an upper surface of the first and second memory modules.

公开(公告)号：US11133261B2

公开(公告)日：2021-09-28

申请号：US15845336

申请日：2017-12-18

申请人： Intel Corporation

发明人： Eng Huat Goh ,  Min Suet Lim ,  Chee Kheong Yoon ,  Jia Yan Go

IPC分类号： H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H01L25/00 ,  H01L25/18 ,  H01L23/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31

摘要： An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.

公开(公告)号：US11006514B2

公开(公告)日：2021-05-11

申请号：US16481043

申请日：2017-03-30

申请人： Intel Corporation

发明人： Jia Yan Go ,  Min Suet Lim ,  Tin Poay Chuah ,  Seok Ling Lim ,  Howe Yin Loo

IPC分类号： H01L23/552 ,  H05K1/02 ,  H01L21/50 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11 ,  H05K1/18 ,  H05K3/30 ,  H01L49/02 ,  H01L23/64

摘要： Semiconductor packages and a method of forming a semiconductor package are described. The semiconductor package has a foundation layer mounted on a motherboard. The semiconductor package also includes a hole in motherboard (HiMB) that is formed in the motherboard. The semiconductor package has one or more capacitors mounted on an electrical shield. The electrical shield may be embedded in the HiMB of the motherboard. Accordingly, the semiconductor package has capacitors vertically embedded between the electrical shield and the HiMB of the motherboard. The semiconductor package may also have one or more HiMB sidewalls formed on the HiMB, where each of the one or more HiMB sidewalls includes at least one or more plated through holes (PTHs) with an exposed layer. The PTHs may be electrically coupled to the capacitors as the capacitors are vertically embedded between the electrical shield sidewalls and the HiMB sidewalls (i.e., three-dimensional (3D) capacitors).

公开(公告)号：US20190364702A1

公开(公告)日：2019-11-28

申请号：US16535766

申请日：2019-08-08

申请人： Intel Corporation

发明人： Min Suet Lim ,  Yew San Lim ,  Jia Yan Go ,  Tin Poay Chuah ,  Eng Huat Goh

IPC分类号： H05K9/00 ,  H05K1/11 ,  H05K3/46

摘要： Apparatus and method for providing an electromagnetic interference (EMI) shield for removable engagement with a printed circuit board (PCB). A shaped electrically conductive member has a substantially planar member portion with multiple lateral member edges. The sidewalls are disposed at respective lateral member edges and are substantially orthogonal to the substantially planar member portion. At least one of the sidewalls includes at least one first snap-fit latching feature to engage a respective complementary second snap-fit latching feature disposed at one or more of multiple peripheral portions of a PCB.