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公开(公告)号：US20170257121A1
公开(公告)日：2017-09-07
申请号：US15059642
申请日：2016-03-03
Applicant: Intel Corporation
Inventor： Zion S. Kwok
CPC classification number: H03M13/2927 , G06F11/1012 , G06F11/1076 , H03M13/1105 , H03M13/1108 , H03M13/3746 , H03M13/3761 , H03M13/451 , H03M13/458
Abstract: Technologies for correcting flipped bits prior to performing an error correction decode process include an apparatus that includes a memory to store a redundant set of codewords and a controller to read data from the memory. The controller selects a codeword from the redundant set of codewords to read from the memory, analyzes the selected codewords to determine whether the codeword contains uncorrectable errors, reads remaining codewords in the redundant set that correspond to the selected codeword, combines the remaining codewords together to generate a rebuilt codeword, flips bits in sections of the rebuilt codeword that differ from the selected codeword by a threshold amount, and performs an error correction decode process based on the rebuilt codeword.
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公开(公告)号：US20160283325A1
公开(公告)日：2016-09-29
申请号：US14671960
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Zion S. Kwok
CPC classification number: H03M13/617 , G06F11/1012 , G06F11/108 , H03M13/1515 , H03M13/154 , H03M13/1545 , H03M13/3761
Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.
Abstract translation: 实施例通常针对从多个存储器件进行的错误和擦除解码。 装置可以包括用于存储多个存储器件中的每一个中的纠错码字的一部分的逻辑，以及用于解码存储器件的错误和擦除的逻辑。 误差和擦除的解码包括从存储器件的子集读取纠错码字的部分以生成部分码字，其中该子集排除了至少一个存储器件。 错误和擦除的解码还包括至少部分地基于部分码字来解码多个存储器件的错误和擦除，如果错误和擦除可以从部分代码字解码，并且在确定错误和擦除 不能从部分码字解码，然后从从第一子集排除的存储器件中读出纠错码字的一个或多个部分以产生完整的码字。
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公开(公告)号：US20160085692A1
公开(公告)日：2016-03-24
申请号：US14493924
申请日：2014-09-23
Applicant: Intel Corporation
Inventor： Zion S. Kwok
CPC classification number: G06F12/1408 , G06F21/79 , G06F2212/402 , G06F2212/403
Abstract: Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed.
Abstract translation: 描述了存储器中AES完整性检查的装置，系统和方法。 在一个实施例中，控制器包括接收来自主机设备的写请求以将数据行写入存储器设备的逻辑，从数据行确定第一明文循环冗余校验，加密数据行，加密第一 具有唯一值的明文CRC以生成第一加密CRC，并将加密的数据行和第一加密CRC存储在存储器中。 还公开并要求保护其他实施例。
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34.发明授权公开(公告)号：US11657889B2
公开(公告)日：2023-05-23
申请号：US16827235
申请日：2020-03-23
Applicant: Intel Corporation
Inventor： Jawad B. Khan , Richard L. Coulson , Zion S. Kwok , Ravi H. Motwani
CPC classification number: G11C29/42 , G11C5/025 , G11C11/409 , G11C29/021 , G11C29/44 , G11C2029/1204
Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.
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公开(公告)号：US10579473B2
公开(公告)日：2020-03-03
申请号：US15721291
申请日：2017-09-29
Applicant: Intel Corporation
Inventor： Santhosh K. Vanaparthy , Ravi H. Motwani , Zion S. Kwok
Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.
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Patent Agency Ranking
公开(公告)号：US10310989B2
公开(公告)日：2019-06-04
申请号：US15721379
申请日：2017-09-29
Applicant: INTEL CORPORATION
Inventor： Philip Hillier , Jeffrey W. Ryden , Muthukumar P. Swaminathan , Zion S. Kwok , Kunal A. Khochare , Richard P. Mangold , Prashant S. Damle
IPC: G06F12/126 , G06F12/02 , G11C7/22
Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.
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公开(公告)号：US10256842B2
公开(公告)日：2019-04-09
申请号：US15059642
申请日：2016-03-03
Applicant: Intel Corporation
Inventor： Zion S. Kwok
Abstract: Technologies for correcting flipped bits prior to performing an error correction decode process include an apparatus that includes a memory to store a redundant set of codewords and a controller to read data from the memory. The controller selects a codeword from the redundant set of codewords to read from the memory, analyzes the selected codewords to determine whether the codeword contains uncorrectable errors, reads remaining codewords in the redundant set that correspond to the selected codeword, combines the remaining codewords together to generate a rebuilt codeword, flips bits in sections of the rebuilt codeword that differ from the selected codeword by a threshold amount, and performs an error correction decode process based on the rebuilt codeword.
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公开(公告)号：US20170186500A1
公开(公告)日：2017-06-29
申请号：US14998240
申请日：2015-12-23
Applicant: INTEL CORPORATION
Inventor： Ravi H. Motwani , Zion S. Kwok , Poovaiah M. Palangappa
CPC classification number: G06F11/1612 , G11C16/26 , G11C29/12 , G11C29/42 , G11C29/4401 , H03M13/05 , H03M13/1102 , H03M13/19 , H03M13/23 , H03M13/2906 , H03M13/2909 , H03M13/2918 , H03M13/2957
Abstract: Memory circuit defect correction in accordance with one aspect of the present description, logically divides a block of data bits into a plurality of data bit sections, each data bit section to be written into and stored in an associated memory section of a block of memory logically divided into a plurality memory sections. In one embodiment, for each data bit section and its associated memory section, the logical values of all the user data bits of the data bit section are selectively flipped so that the logical value of a user data bit to be written into a defective bitcell, matches the fixed read output of a defective bit cell. A bitcell in each memory section may be utilized to set a flip-flag to indicate whether or not the data bits of the memory section have been flipped. Other aspects are described herein.
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公开(公告)号：US09680509B2
公开(公告)日：2017-06-13
申请号：US14671960
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Zion S. Kwok
CPC classification number: H03M13/617 , G06F11/1012 , G06F11/108 , H03M13/1515 , H03M13/154 , H03M13/1545 , H03M13/3761
Abstract: Embodiments are generally directed to errors and erasures decoding from multiple memory devices. An apparatus may include logic to store a portion of an error correction codeword in each of multiple memory devices, and logic to decode errors and erasures for the memory devices. The decoding of the errors and erasures includes reading the portions of the error correction codeword from a subset of the memory devices to generate a partial codeword, with the subset excluding at least one of the memory devices. The decoding of the errors and erasures further includes decoding errors and erasures of the plurality of memory devices based at least in part on the partial codeword if the errors and erasures can be decoded from the partial codeword, and, upon determining that the errors and erasures cannot be decoded from the partial codeword, then reading the one or more portions of the error correction codeword from the memory devices excluded from the first subset to generate a complete codeword.
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公开(公告)号：US09588882B2
公开(公告)日：2017-03-07
申请号：US14094743
申请日：2013-12-02
Applicant: Intel Corporation
Inventor： Scott E. Nelson , Zion S. Kwok
CPC classification number: G06F12/0238 , G06F3/06 , G06F12/04 , Y02D10/13
Abstract: Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a rotation value prior to storage of the one or more sectors in a non-volatile memory device. Logic then rotates the one or more sectors back by the rotation value after reading the one or more sectors from the non-volatile memory device. Furthermore, at least one indirection block (corresponding to the one or more sectors) is stored in at least two different logical memory pages of the non-volatile memory. Other embodiments are also disclosed and claimed.
Abstract translation: 描述与非易失性存储器页扇区旋转相关的方法和装置。 在一个实施例中，逻辑在将一个或多个扇区存储在非易失性存储器设备中之前将一个或多个扇区的顺序旋转一个旋转值。 逻辑然后在从非易失性存储器件读取一个或多个扇区之后使一个或多个扇区回转旋转值。 此外，至少一个间接块（对应于一个或多个扇区）被存储在非易失性存储器的至少两个不同的逻辑存储器页中。 还公开并要求保护其他实施例。
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